The addr_i signal of the iob_cache_control component does not contain the 2 least significant bits of the register addresses.
Therefore, the reference addresses must also be shifted by 2.
The register addresses should also be separated from each other by 4, to allow the iob_cache_control to know which register is being written to.
Note, the addr_i signal does not contain the 2 least significant bits, because the front end and other components don't use them, based on the value o the parameter FE_NBYTES_W. If the value of this parameter changes, so will the number of least significant bits discarded. So this solution may not for all cases!
The
addr_isignal of theiob_cache_controlcomponent does not contain the 2 least significant bits of the register addresses. Therefore, the reference addresses must also be shifted by 2. The register addresses should also be separated from each other by 4, to allow theiob_cache_controlto know which register is being written to.Note, the
addr_isignal does not contain the 2 least significant bits, because the front end and other components don't use them, based on the value o the parameterFE_NBYTES_W. If the value of this parameter changes, so will the number of least significant bits discarded. So this solution may not for all cases!