The verilator testbench didn't work as the author had intended - no data was written to or read from the cache and it also never printed any messages like Reading rdata=0x0 at addr=0x0: PASSED. But the test would still pass with a "Test passed!" message. I've changed the testbench and I believe it now works as intendend.
There was one big while loop which contained four blocks: For writing, reading, incrementing counters and validating the read data. But the write and read blocks were always followed by the incrementing block, which would then set dut->iob_valid_i = 0 before any simulation time could pass. This also caused dut->iob_rvalid_o to never be true and so the read data validation block was never entered. I've now changed the testbench to not use one big while loop.
jjts
commented
5 months ago
The verilator testbench didn't work as the author had intended - no data was written to or read from the cache and it also never printed any messages like
Reading rdata=0x0 at addr=0x0: PASSED. But the test would still pass with a "Test passed!" message. I've changed the testbench and I believe it now works as intendend.There was one big while loop which contained four blocks: For writing, reading, incrementing counters and validating the read data. But the write and read blocks were always followed by the incrementing block, which would then set
dut->iob_valid_i = 0before any simulation time could pass. This also causeddut->iob_rvalid_oto never be true and so the read data validation block was never entered. I've now changed the testbench to not use one big while loop.