Improvements in write_process_native module: was having a 1-clock-cycle unecessary stall.
fix write_process_axi: in a illegal write, it was actually updating the FIFO, instead of just re-transfering.
Added LRU with shifts (still uses more logic than the adders, was added only for the thesis, in case they may ask).
Improvements in write_process_native module: was having a 1-clock-cycle unecessary stall. fix write_process_axi: in a illegal write, it was actually updating the FIFO, instead of just re-transfering. Added LRU with shifts (still uses more logic than the adders, was added only for the thesis, in case they may ask).