Some additional changes to cache-memory.v, added pipelined testbench.

IObundle / iob-cache

Verilog Configurable Cache

MIT License

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Closed joaovroque closed 4 years ago

joaovroque commented 4 years ago

Some changes to both cache-memory and back-end.
added pipeline testbench (similar on how a pipelined architecture processor would work.
still some data-flow problems, some signals are asserting too soon.