joaovroque
commented
4 years ago - Cache-memory (cache_memory.v) has all the available configurations for N_WAYS and LINE2MEM_W paramaters.
- For LINE2MEM_W = 0 may require some optimization, as synthesis results resulted in an unwanted increase in LUTs (around 200, need to check the reason (was expecting around the same or even less (the only difference is that the back-end write-channel has MUX to align both wdata and wstrb, but the remaining logic in the read-channel and in cache-memory gets simpler)).