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IObundle / iob-cache

Verilog Configurable Cache
MIT License
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make sim #92

Closed tnvikramatgmail closed 3 years ago

tnvikramatgmail commented 3 years ago

CACHE_DIR:=. include ./core.mk

sim: make -C $(CACHE_SIM_DIR) all

Had to add an all in the Makefile, otherwise the make sim would output a string called CACHE

jjts commented 3 years ago

Thanks! It's been added to the master branch, though iob-soc is still using an older commit. Just do

git pull origin master && git submodule update --init ---recursive

Closing.