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iob-eth
Basic Verilog Ethernet core and C driver functions
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feat(mkregs): update LIB submodule, fix core sim
#41
Closed
P-Miranda
closed
2 years ago
P-Miranda
commented
2 years ago
update LIB submodule
update core logic, instanted and core testbench accordingly
passes
make sim
core testbench
integration working on [d5e0036324] commit from IObundle/iob-soc
see IObundle/iob-lib#103
make sim
core testbench