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IObundle / iob-soc

RISC-V System on Chip Template
MIT License
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VCD=1 blocks simulation #431

Closed jjts closed 2 years ago

jjts commented 2 years ago

make sim-run SIMULATOR=xcelium RUN_EXTMEM=1 VCD=0 INIT_MEM=0

Works well .

Activating VCD with

make sim-run SIMULATOR=xcelium RUN_EXTMEM=1 VCD=1 INIT_MEM=0

causes simulation to hang when sending the firmware back to the PC via console. It is also curious that, in general, receiving files via uart takes a lot less time than sending.

This can't be a Verilog bug as it works fine for VCD=0. It is the fact that VCD=1 makes simulation slower that excites a bug in the communication tb --> console, via file transfer.

jjts commented 2 years ago

With Icarus, it is more likely to hang, even without VCD=1, because Icarus is slower.

jjts commented 2 years ago

reported as solved by J.Lopes