Support multiple clocks for Verilator Simulation

IObundle / iob-soc

RISC-V System on Chip Template

MIT License

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Open P-Miranda opened 1 day ago

P-Miranda commented 1 day ago

Verilator simulation toggles clocks from function Timer() in iob_tasks.cpp and only supports a single hardcoded clk.

Update iob_tasks.cpp to support multiple clocks
or add pointer to custom Timer() function that can be implemented in iob_soc_tb.cpp or equivalent top level testbench for verilator.

This applies to all branches and relates to .cpp files that are not directly affected by if_gen2 developments.

jjts commented 1 day ago

We have tried this before; isn't there a timing directive that causes issues?