Add `parent` attribute; Add bit slicing and concatenations in port connections; Add regfile in CSRs and asym FIFOs. - Githubissues

IObundle / py2hwsw

a Python framework for managing embedded HW/SW projects

MIT License

9 stars 3 forks source link

Add `parent` attribute; Add bit slicing and concatenations in port connections; Add regfile in CSRs and asym FIFOs. #50

Closed arturum1 closed 1 month ago

arturum1 commented 1 month ago

See commits for details.

Used in PR https://github.com/IObundle/iob-soc/pull/953