upgrade AXI interconnect to multi-split / multi-merge architecture

[jjts]

This will allow masters M1 and M2 to access slaves S1 and S2, respectively, in parallel!

Generate a customer AXI interconnect where

• each master only splits to the salves it needs to access
• each slave only merges the masters that access it

Due to the shallower depth of this new interconnect, an improvement in clock frequency is expected but the occupied area will be higher