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Illusive7Man / WallaceTreeAdder

Generates a Verilog implementation of a Wallace tree of 3-2 carry save adders.
MIT License
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condition and file output #1

Open Griffintaur opened 3 years ago

Griffintaur commented 3 years ago
  1. Is there any condition on number of operands and operand's bit-length
  2. the output file being generated is wallace_stimulus.txt, not wallace_testbench?
Illusive7Man commented 3 years ago

Answer 1.: There's no upper limit, and there probably isn't a lower one either. I am not sure. Answer 2.: You are correct.