I'm trying to get this up and running on a Jetson Nano development kit with the Auvidea B112 HDMI to CSI-2 Bridge. I've managed to update the LT6911UXC kernel driver from the source in this repo. I've updated the device tree using the text file in this repo as a guide. I can see the driver probe function being called and executing successfully in the kernel log - it clearly states that the I2C device has been found correctly. I also have /dev/video0 present and v4l2-ctl --all returns all the expected device information.
When I start a video pipeline I get the following printed in the kernel log for every frame
kernel: [ 437.311273] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 0
kernel: [ 437.327941] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 1
kernel: [ 437.344593] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 2
...
I suspect this may be to do with the Jetson Nano dev kit only having a 2-lane MIPI CSI connector, while the LT6911UXC reports that it is configured for 4-lanes. Are there any instructions for configuring the LT6911UXC for 2-lane operation? I've tried manually setting the I2C register (which represents the number of MIPI lanes) from 4 to 2. While this is retained by the chip, it appears to have no effect.
I'm trying to get this up and running on a Jetson Nano development kit with the Auvidea B112 HDMI to CSI-2 Bridge. I've managed to update the LT6911UXC kernel driver from the source in this repo. I've updated the device tree using the text file in this repo as a guide. I can see the driver probe function being called and executing successfully in the kernel log - it clearly states that the I2C device has been found correctly. I also have /dev/video0 present and
v4l2-ctl --allreturns all the expected device information.When I start a video pipeline I get the following printed in the kernel log for every frame
I suspect this may be to do with the Jetson Nano dev kit only having a 2-lane MIPI CSI connector, while the LT6911UXC reports that it is configured for 4-lanes. Are there any instructions for configuring the LT6911UXC for 2-lane operation? I've tried manually setting the I2C register (which represents the number of MIPI lanes) from 4 to 2. While this is retained by the chip, it appears to have no effect.