Infineon / psoc4hal

The Cypress PSoC 4 Hardware Abstraction Layer (HAL) provides a high-level interface to configure and use hardware blocks on Cypress MCUs.
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Unable to build library with warnings-as-errors enabled #2

Closed gtaska closed 3 years ago

gtaska commented 3 years ago

Prerequisites

Can you reproduce the problem reliably? Yes

Did you check current release notes for known issues? No, but checked for issue in master/HEAD

If this is not the latest release, have you checked newer releases? Issue is in master/HEAD

Description:

I want to fail my builds if any warnings occur, however I am unable to turn on the 'warning-as-errors' compiler flags because the PSOC4 Hal library doesn't compile cleanly without warnings.

Steps to Reproduce:

  1. Enable 'warnings-as-errors' (CFLAGS= -Werror and CXXFLAGS= -Werror)

  2. Build

  3. Build fails.

In file included from libs/psoc4hal/COMPONENT_PSOC4HAL/source/cyhal_clock.c:27:
libs/psoc4hal/COMPONENT_PSOC4HAL/source/cyhal_clock.c: In function 'cyhal_clock_set_divider':
./libs/psoc4pdl/drivers/include/cy_sysclk.h:1241:8: error: 'new_div' may be used uninitialized in this function [-Werror=maybe-uninitialized]
 1241 |     if (CY_SYSCLK_IS_DIV_VALID(divider))
      |        ^
libs/psoc4hal/COMPONENT_PSOC4HAL/source/cyhal_clock.c:695:37: note: 'new_div' was declared here
  695 |             cy_en_sysclk_dividers_t new_div;
      |                                     ^~~~~~~
    Compiling app file cyhal_timer.c
    Compiling app file cyhal_uart.c

In this case, not all return paths in cyhal_get_sysclk_div initialize the div parameter...

https://github.com/cypresssemiconductorco/psoc4hal/blob/4eab0fbf6470e05193e8c9703642d6b84acaf844/COMPONENT_PSOC4HAL/source/cyhal_clock.c#L143-L163

... and the returned result is not checked before calling Cy_SysClk_ClkSysSetDivider(new_div).

https://github.com/cypresssemiconductorco/psoc4hal/blob/4eab0fbf6470e05193e8c9703642d6b84acaf844/COMPONENT_PSOC4HAL/source/cyhal_clock.c#L695-L697

(This is not a problem in cyhal_set_hfclk_div, as the return code is checked before attempting to use new_div).

Expected Result:

I should be able to build the supplied code without any warnings.

This particular problem can be 'fixed' with the following tweak to line 696:

        if (CY_RSLT_SUCCESS == rslt) Cy_SysClk_ClkSysSetDivider(new_div);

Actual Result:

Build fails if warnings-as-errors are turned on.

Frequency (1/1, 1/50, 1/100):

1/1

Build/Commit:

master/Head (4eab0fbf6470e05193e8c9703642d6b84acaf844)

Target:

CY8C4146LQI-S422

Host OS and Version:

Win10

Compiler:

GCC included in ModusToolbox 2.1

rmbk19 commented 3 years ago

Hi @gtaska,

psoc4hal library was released as part of alpha content for PSoC 4 devices. With the official release of PSoC 4 devices on ModusToolbox, the PSoC 4 BSPs uses mtb-hal-cat2. Can you try updating to ModusToolbox 2.2 and build a project for PSoC 4? This should use the latest release and build successfully.

Thanks and Regards, Rakshith M B

gtaska commented 3 years ago

Thanks for the pointer.

BTW, I would suggest that Cypress do a better job at communicating what cat2, cat1, cat1a etc are. I am starting to see these terms used, but have no reference about what they mean.

rmbk19 commented 3 years ago

Hi @gtaska,

As this information is specific to the library, it is mentioned in the About section of the library in the repository as shown - image

Additionally, this information about the library can also be found in the Library Manager - image

But if you have any suggestions as to how we can communicate this better to make it easier for users, please let me know. I will forward your suggestion to our internal team so that they can evaluate your request.

Regards, Rakshith