Bad flash, tons of log spam, etc

[codefaux]

Hi there. Just downloaded and used v1.1 (I think, there's no clear version indication on the software anywhere I can find) on a factory-new ESP32-Cam module with a freshly downloaded tasmota32-webcam.bin firmware.

It seemed to do the usual work, but after finishing the Console window was scrolling VOLUMES of random characters occasionally tagged with a timestamp and sometimes a few other lines I couldn't read. I couldn't stop the scrolling lines; they were CONSTANTLY churning past.

The only way I could find to interrupt it was to unplug the device, which caused the application to instantly crash and disappear.

I tried again a second time, but this time it was vomiting text I couldn't read (or log, or stop, or slow down) over and over and over and over and over .....so I unplugged the device again, and tried a third time.

Same results.

After that, I manually downloaded all of the files from the Tasmota Github and manually flashed it using the following command; esptool.py --chip esp32 --port COM9 --baud 921600 --before default_reset --after hard_reset write_flash -z --flash_mode dout --flash_freq 40m --flash_size detect 0x1000 bootloader_dout_40m.bin 0x8000 partitions.bin 0xe000 boot_app0.bin 0x10000 tasmota32-webcam.bin

Manually flashing worked fine. Reflashing with ESP_Flasher AFTER manually flashing results in the exact same behavior -- repeated, scrolling, spamming text that goes past so fast I can't read it.

I'd love to give more information, but the application doesn't leave logs behind to examine.

[codefaux]

Oh hey this time it didn't crash instantly when I unplugged the device in a desperate attempt to make the application stop spamming and close. Here you go.

`Using 'COM9' as serial port. Connecting..... Detecting chip type... ESP32 Connecting....

Chip Info:

• Chip Family: ESP32
• Chip Model: ESP32-D0WDQ6 (revision 1)
• Number of Cores: 2
• Max CPU Frequency: 240MHz
• Has Bluetooth: YES
• Has Embedded Flash: NO
• Has Factory-Calibrated ADC: YES
• MAC Address: 84:CC:A8:7B:9D:C8 Uploading stub... Running stub... Stub running... Changing baud rate to 460800 Changed.
• Flash Size: 4MB
• Flash Mode: qio
• Flash Frequency: 80MHz Erasing flash (this may take a while)... Chip erase completed successfully in 3.2s Flash params set to 0x002f Compressed 18656 bytes to 12053... Writing at 0x00001000... (100 %) Wrote 18656 bytes (12053 compressed) at 0x00001000 in 0.3 seconds (effective 550.3 kbit/s)... Hash of data verified. Compressed 3072 bytes to 129... Writing at 0x00008000... (100 %) Wrote 3072 bytes (129 compressed) at 0x00008000 in 0.0 seconds (effective 4436.6 kbit/s)... Hash of data verified. Compressed 8192 bytes to 47... Writing at 0x0000e000... (100 %) Wrote 8192 bytes (47 compressed) at 0x0000e000 in 0.0 seconds (effective 21705.5 kbit/s)... Hash of data verified. Compressed 1425152 bytes to 832040... Writing at 0x00010000... (1 %) Writing at 0x00014000... (3 %) Writing at 0x00018000... (5 %) Writing at 0x0001c000... (7 %) Writing at 0x00020000... (9 %) Writing at 0x00024000... (11 %) Writing at 0x00028000... (13 %) Writing at 0x0002c000... (15 %) Writing at 0x00030000... (17 %) Writing at 0x00034000... (19 %) Writing at 0x00038000... (21 %) Writing at 0x0003c000... (23 %) Writing at 0x00040000... (25 %) Writing at 0x00044000... (27 %) Writing at 0x00048000... (29 %) Writing at 0x0004c000... (31 %) Writing at 0x00050000... (33 %) Writing at 0x00054000... (35 %) Writing at 0x00058000... (37 %) Writing at 0x0005c000... (39 %) Writing at 0x00060000... (41 %) Writing at 0x00064000... (43 %) Writing at 0x00068000... (45 %) Writing at 0x0006c000... (47 %) Writing at 0x00070000... (49 %) Writing at 0x00074000... (50 %) Writing at 0x00078000... (52 %) Writing at 0x0007c000... (54 %) Writing at 0x00080000... (56 %) Writing at 0x00084000... (58 %) Writing at 0x00088000... (60 %) Writing at 0x0008c000... (62 %) Writing at 0x00090000... (64 %) Writing at 0x00094000... (66 %) Writing at 0x00098000... (68 %) Writing at 0x0009c000... (70 %) Writing at 0x000a0000... (72 %) Writing at 0x000a4000... (74 %) Writing at 0x000a8000... (76 %) Writing at 0x000ac000... (78 %) Writing at 0x000b0000... (80 %) Writing at 0x000b4000... (82 %) Writing at 0x000b8000... (84 %) Writing at 0x000bc000... (86 %) Writing at 0x000c0000... (88 %) Writing at 0x000c4000... (90 %) Writing at 0x000c8000... (92 %) Writing at 0x000cc000... (94 %) Writing at 0x000d0000... (96 %) Writing at 0x000d4000... (98 %) Writing at 0x000d8000... (100 %) Wrote 1425152 bytes (832040 compressed) at 0x00010000 in 18.8 seconds (effective 607.4 kbit/s)... Hash of data verified.

Leaving... Hard Resetting... Done! Flashing is complete!

Showing logs: [17:26:03]ets Jun 8 2016 00:22:57 [17:26:03] [17:26:03]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:03]configsip: 0, SPIWP:0xee [17:26:03]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:03]mode:QIO, clock div:1 [17:26:03]load:0x3fff0018,len:4 [17:26:03]load:0x928b2121,len:-1725455839 [17:26:03]1162 mmu set 00010000, pos 00010000 [17:26:03]1162 mmu set 00020000, pos 00020000 [17:26:03]1162 mmu set 00030000, pos 00030000 [17:26:03]1162 mmu set 00040000, pos 00040000 [17:26:03]1162 mmu set 00050000, pos 00050000 [17:26:03]1162 mmu set 00060000, pos 00060000 [17:26:03]1162 mmu set 00070000, pos 00070000 [17:26:03]1162 mmu set 00080000, pos 00080000 [17:26:03]1162 mmu set 00090000, pos 00090000 [17:26:03]1162 mmu set 000a0000, pos 000a0000 [17:26:03]1162 mmu set 000b0000, pos 000b0000 [17:26:03]1162 mmu set 000c0000, pos 000c0000 [17:26:03]1162 mmu set 000d0000, pos 000d0000 [17:26:03]1162 mmu set 000e0000, pos 000e0000 [17:26:03]1162 mmu set 000f0000, pos 000f0000 [17:26:03]1162 mmu set 00100000, pos 00100000 [17:26:03]1162 mmu set 00110000, pos 00110000 [17:26:03]ets Jun 8 2016 00:22:57 [17:26:03] [17:26:03]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:03]configsip: 0, SPIWP:0xee [17:26:03]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:03]mode:QIO, clock div:1 [17:26:03]load:0x3fff0018,len:4 [17:26:03]load:0x928b2121,len:-1725455839 [17:26:03]1162 mmu set 00010000, pos 00010000 [17:26:03]1162 mmu set 00020000, pos 00020000 [17:26:03]1162 mmu set 00030000, pos 00030000 [17:26:03]1162 mmu set 00040000, pos 00040000 [17:26:03]1162 mmu set 00050000, pos 00050000 [17:26:04]1162 mmu set 00060000, pos 00060000 [17:26:04]1162 mmu set 00070000, pos 00070000 [17:26:04]1162 mmu set 00080000, pos 00080000 [17:26:04]1162 mmu set 00090000, pos 00090000 [17:26:04]1162 mmu set 000a0000, pos 000a0000 [17:26:04]1162 mmu set 000b0000, pos 000b0000 [17:26:04]1162 mmu set 000c0000, pos 000c0000 [17:26:04]1162 mmu set 000d0000, pos 000d0000 [17:26:04]1162 mmu set 000e0000, pos 000e0000 [17:26:04]1162 mmu set 000f0000, pos 000f0000 [17:26:04]1162 mmu set 00100000, pos 00100000 [17:26:04]1162 mmu set 00110000, pos 00110000 [17:26:04]ets Jun 8 2016 00:22:57 [17:26:04] [17:26:04]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:04]configsip: 0, SPIWP:0xee [17:26:04]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:04]mode:QIO, clock div:1 [17:26:04]load:0x3fff0018,len:4 [17:26:04]load:0x928b2121,len:-1725455839 [17:26:04]1162 mmu set 00010000, pos 00010000 [17:26:04]1162 mmu set 00020000, pos 00020000 [17:26:04]1162 mmu set 00030000, pos 00030000 [17:26:04]1162 mmu set 00040000, pos 00040000 [17:26:04]1162 mmu set 00050000, pos 00050000 [17:26:04]1162 mmu set 00060000, pos 00060000 [17:26:04]1162 mmu set 00070000, pos 00070000 [17:26:04]1162 mmu set 00080000, pos 00080000 [17:26:04]1162 mmu set 00090000, pos 00090000 [17:26:04]1162 mmu set 000a0000, pos 000a0000 [17:26:04]1162 mmu set 000b0000, pos 000b0000 [17:26:04]1162 mmu set 000c0000, pos 000c0000 [17:26:04]1162 mmu set 000d0000, pos 000d0000 [17:26:04]1162 mmu set 000e0000, pos 000e0000 [17:26:04]1162 mmu set 000f0000, pos 000f0000 [17:26:04]1162 mmu set 00100000, pos 00100000 [17:26:04]1162 mmu set 00110000, pos 00110000 [17:26:04]ets Jun 8 2016 00:22:57 [17:26:04] [17:26:04]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:04]configsip: 0, SPIWP:0xee [17:26:04]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:04]mode:QIO, clock div:1 [17:26:04]load:0x3fff0018,len:4 [17:26:04]load:0x928b2121,len:-1725455839 [17:26:04]1162 mmu set 00010000, pos 00010000 [17:26:04]1162 mmu set 00020000, pos 00020000 [17:26:04]1162 mmu set 00030000, pos 00030000 [17:26:04]1162 mmu set 00040000, pos 00040000 [17:26:04]1162 mmu set 00050000, pos 00050000 [17:26:04]1162 mmu set 00060000, pos 00060000 [17:26:04]1162 mmu set 00070000, pos 00070000 [17:26:04]1162 mmu set 00080000, pos 00080000 [17:26:04]1162 mmu set 00090000, pos 00090000 [17:26:04]1162 mmu set 000a0000, pos 000a0000 [17:26:04]1162 mmu set 000b0000, pos 000b0000 [17:26:04]1162 mmu set 000c0000, pos 000c0000 [17:26:04]1162 mmu set 000d0000, pos 000d0000 [17:26:04]1162 mmu set 000e0000, pos 000e0000 [17:26:04]1162 mmu set 000f0000, pos 000f0000 [17:26:04]1162 mmu set 00100000, pos 00100000 [17:26:04]1162 mmu set 00110000, pos 00110000 [17:26:04]ets Jun 8 2016 00:22:57 [17:26:04] [17:26:04]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:04]configsip: 0, SPIWP:0xee [17:26:05]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:05]mode:QIO, clock div:1 [17:26:05]load:0x3fff0018,len:4 [17:26:05]load:0x928b2121,len:-1725455839 [17:26:05]1162 mmu set 00010000, pos 00010000 [17:26:05]1162 mmu set 00020000, pos 00020000 [17:26:05]1162 mmu set 00030000, pos 00030000 [17:26:05]1162 mmu set 00040000, pos 00040000 [17:26:05]1162 mmu set 00050000, pos 00050000 [17:26:05]1162 mmu set 00060000, pos 00060000 [17:26:05]1162 mmu set 00070000, pos 00070000 [17:26:05]1162 mmu set 00080000, pos 00080000 [17:26:05]1162 mmu set 00090000, pos 00090000 [17:26:05]1162 mmu set 000a0000, pos 000a0000 [17:26:05]1162 mmu set 000b0000, pos 000b0000 [17:26:05]1162 mmu set 000c0000, pos 000c0000 [17:26:05]1162 mmu set 000d0000, pos 000d0000 [17:26:05]1162 mmu set 000e0000, pos 000e0000 [17:26:05]1162 mmu set 000f0000, pos 000f0000 [17:26:05]1162 mmu set 00100000, pos 00100000 [17:26:05]1162 mmu set 00110000, pos 00110000 [17:26:05]ets Jun 8 2016 00:22:57 [17:26:05] [17:26:05]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:05]configsip: 0, SPIWP:0xee [17:26:05]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:05]mode:QIO, clock div:1 [17:26:05]load:0x3fff0018,len:4 [17:26:05]load:0x928b2121,len:-1725455839 [17:26:05]1162 mmu set 00010000, pos 00010000 [17:26:05]1162 mmu set 00020000, pos 00020000 [17:26:05]1162 mmu set 00030000, pos 00030000 [17:26:05]1162 mmu set 00040000, pos 00040000 [17:26:05]1162 mmu set 00050000, pos 00050000 [17:26:05]1162 mmu set 00060000, pos 00060000 [17:26:05]1162 mmu set 00070000, pos 00070000 [17:26:05]1162 mmu set 00080000, pos 00080000 [17:26:05]1162 mmu set 00090000, pos 00090000 [17:26:05]1162 mmu set 000a0000, pos 000a0000 [17:26:05]1162 mmu set 000b0000, pos 000b0000 [17:26:05]1162 mmu set 000c0000, pos 000c0000 [17:26:05]1162 mmu set 000d0000, pos 000d0000 [17:26:05]1162 mmu set 000e0000, pos 000e0000 [17:26:05]1162 mmu set 000f0000, pos 000f0000 [17:26:05]1162 mmu set 00100000, pos 00100000 [17:26:05]1162 mmu set 00110000, pos 00110000 [17:26:05]ets Jun 8 2016 00:22:57 [17:26:05] [17:26:05]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:05]configsip: 0, SPIWP:0xee [17:26:05]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:05]mode:QIO, clock div:1 [17:26:05]load:0x3fff0018,len:4 [17:26:05]load:0x928b2121,len:-1725455839 [17:26:05]1162 mmu set 00010000, pos 00010000 [17:26:05]1162 mmu set 00020000, pos 00020000 [17:26:05]1162 mmu set 00030000, pos 00030000 [17:26:05]1162 mmu set 00040000, pos 00040000 [17:26:05]1162 mmu set 00050000, pos 00050000 [17:26:05]1162 mmu set 00060000, pos 00060000 [17:26:05]1162 mmu set 00070000, pos 00070000 [17:26:05]1162 mmu set 00080000, pos 00080000 [17:26:05]1162 mmu set 00090000, pos 00090000 [17:26:05]1162 mmu set 000a0000, pos 000a0000 [17:26:05]1162 mmu set 000b0000, pos 000b0000 [17:26:05]1162 mmu set 000c0000, pos 000c0000 [17:26:06]1162 mmu set 000d0000, pos 000d0000 [17:26:06]1162 mmu set 000e0000, pos 000e0000 [17:26:06]1162 mmu set 000f0000, pos 000f0000 [17:26:06]1162 mmu set 00100000, pos 00100000 [17:26:06]1162 mmu set 00110000, pos 00110000 [17:26:06]ets Jun 8 2016 00:22:57 [17:26:06] [17:26:06]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:06]configsip: 0, SPIWP:0xee [17:26:06]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:06]mode:QIO, clock div:1 [17:26:06]load:0x3fff0018,len:4 [17:26:06]load:0x928b2121,len:-1725455839 [17:26:06]1162 mmu set 00010000, pos 00010000 [17:26:06]1162 mmu set 00020000, pos 00020000 [17:26:06]1162 mmu set 00030000, pos 00030000 [17:26:06]1162 mmu set 00040000, pos 00040000 [17:26:06]1162 mmu set 00050000, pos 00050000 [17:26:06]1162 mmu set 00060000, pos 00060000 [17:26:06]1162 mmu set 00070000, pos 00070000 [17:26:06]1162 mmu set 00080000, pos 00080000 [17:26:06]1162 mmu set 00090000, pos 00090000 [17:26:06]1162 mmu set 000a0000, pos 000a0000 [17:26:06]1162 mmu set 000b0000, pos 000b0000 [17:26:06]1162 mmu set 000c0000, pos 000c0000 [17:26:06]1162 mmu set 000d0000, pos 000d0000 [17:26:06]1162 mmu set 000e0000, pos 000e0000 [17:26:06]1162 mmu set 000f0000, pos 000f0000 [17:26:06]1162 mmu set 00100000, pos 00100000 [17:26:06]1162 mmu set 00110000, pos 00110000 [17:26:06]ets Jun 8 2016 00:22:57 [17:26:06] [17:26:06]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:06]configsip: 0, SPIWP:0xee [17:26:06]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:06]mode:QIO, clock div:1 [17:26:06]load:0x3fff0018,len:4 [17:26:06]load:0x928b2121,len:-1725455839 [17:26:06]1162 mmu set 00010000, pos 00010000 [17:26:06]1162 mmu set 00020000, pos 00020000 [17:26:06]1162 mmu set 00030000, pos 00030000 [17:26:06]1162 mmu set 00040000, pos 00040000 [17:26:06]1162 mmu set 00050000, pos 00050000 [17:26:06]1162 mmu set 00060000, pos 00060000 [17:26:06]1162 mmu set 00070000, pos 00070000 [17:26:06]1162 mmu set 00080000, pos 00080000 [17:26:06]1162 mmu set 00090000, pos 00090000 [17:26:06]1162 mmu set 000a0000, pos 000a0000 [17:26:06]1162 mmu set 000b0000, pos 000b0000 [17:26:06]1162 mmu set 000c0000, pos 000c0000 [17:26:06]1162 mmu set 000d0000, pos 000d0000 [17:26:06]1162 mmu set 000e0000, pos 000e0000 [17:26:06]1162 mmu set 000f0000, pos 000f0000 [17:26:06]1162 mmu set 00100000, pos 00100000 [17:26:06]1162 mmu set 00110000, pos 00110000 [17:26:06]ets Jun 8 2016 00:22:57 [17:26:06] [17:26:06]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:06]configsip: 0, SPIWP:0xee [17:26:06]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:06]mode:QIO, clock div:1 [17:26:06]load:0x3fff0018,len:4 [17:26:06]load:0x928b2121,len:-1725455839 [17:26:06]1162 mmu set 00010000, pos 00010000 [17:26:06]1162 mmu set 00020000, pos 00020000 [17:26:06]1162 mmu set 00030000, pos 00030000 [17:26:06]1162 mmu set 00040000, pos 00040000 [17:26:06]1162 mmu set 00050000, pos 00050000 [17:26:06]1162 mmu set 00060000, pos 00060000 [17:26:06]1162 mmu set 00070000, pos 00070000 [17:26:07]1162 mmu set 00080000, pos 00080000 [17:26:07]1162 mmu set 00090000, pos 00090000 [17:26:07]1162 mmu set 000a0000, pos 000a0000 [17:26:07]1162 mmu set 000b0000, pos 000b0000 [17:26:07]1162 mmu set 000c0000, pos 000c0000 [17:26:07]1162 mmu set 000d0000, pos 000d0000 [17:26:07]1162 mmu set 000e0000, pos 000e0000 [17:26:07]1162 mmu set 000f0000, pos 000f0000 [17:26:07]1162 mmu set 00100000, pos 00100000 [17:26:07]1162 mmu set 00110000, pos 00110000 [17:26:07]ets Jun 8 2016 00:22:57 [17:26:07] [17:26:07]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:07]configsip: 0, SPIWP:0xee [17:26:07]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:07]mode:QIO, clock div:1 [17:26:07]load:0x3fff0018,len:4 [17:26:07]load:0x928b2121,len:-1725455839 [17:26:07]1162 mmu set 00010000, pos 00010000 [17:26:07]1162 mmu set 00020000, pos 00020000 [17:26:07]1162 mmu set 00030000, pos 00030000 [17:26:07]1162 mmu set 00040000, pos 00040000 [17:26:07]1162 mmu set 00050000, pos 00050000 [17:26:07]1162 mmu set 00060000, pos 00060000 [17:26:07]1162 mmu set 00070000, pos 00070000 [17:26:07]1162 mmu set 00080000, pos 00080000 [17:26:07]1162 mmu set 00090000, pos 00090000 [17:26:07]1162 mmu set 000a0000, pos 000a0000 [17:26:07]1162 mmu set 000b0000, pos 000b0000 [17:26:07]1162 mmu set 000c0000, pos 000c0000 [17:26:07]1162 mmu set 000d0000, pos 000d0000 [17:26:07]1162 mmu set 000e0000, pos 000e0000 [17:26:07]1162 mmu set 000f0000, pos 000f0000 [17:26:07]1162 mmu set 00100000, pos 00100000 [17:26:07]1162 mmu set 00110000, pos 00110000 [17:26:07]ets Jun 8 2016 00:22:57 [17:26:07] [17:26:07]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:07]configsip: 0, SPIWP:0xee [17:26:07]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:07]mode:QIO, clock div:1 [17:26:07]load:0x3fff0018,len:4 [17:26:07]load:0x928b2121,len:-1725455839 [17:26:07]1162 mmu set 00010000, pos 00010000 [17:26:07]1162 mmu set 00020000, pos 00020000 [17:26:07]1162 mmu set 00030000, pos 00030000 [17:26:07]1162 mmu set 00040000, pos 00040000 [17:26:07]1162 mmu set 00050000, pos 00050000 [17:26:07]1162 mmu set 00060000, pos 00060000 [17:26:07]1162 mmu set 00070000, pos 00070000 [17:26:07]1162 mmu set 00080000, pos 00080000 [17:26:07]1162 mmu set 00090000, pos 00090000 [17:26:07]1162 mmu set 000a0000, pos 000a0000 [17:26:07]1162 mmu set 000b0000, pos 000b0000 [17:26:07]1162 mmu set 000c0000, pos 000c0000 [17:26:07]1162 mmu set 000d0000, pos 000d0000 [17:26:07]1162 mmu set 000e0000, pos 000e0000 [17:26:07]1162 mmu set 000f0000, pos 000f0000 [17:26:07]1162 mmu set 00100000, pos 00100000 [17:26:07]1162 mmu set 00110000, pos 00110000 [17:26:07]ets Jun 8 2016 00:22:57 [17:26:07] [17:26:07]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:07]configsip: 0, SPIWP:0xee [17:26:07]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:07]mode:QIO, clock div:1 [17:26:07]load:0x3fff0018,len:4 [17:26:07]load:0x928b2121,len:-1725455839 [17:26:07]1162 mmu set 00010000, pos 00010000 [17:26:07]1162 mmu set 00020000, pos 00020000 [17:26:08]1162 mmu set 00030000, pos 00030000 [17:26:08]1162 mmu set 00040000, pos 00040000 [17:26:08]1162 mmu set 00050000, pos 00050000 [17:26:08]1162 mmu set 00060000, pos 00060000 [17:26:08]1162 mmu set 00070000, pos 00070000 [17:26:08]1162 mmu set 00080000, pos 00080000 [17:26:08]1162 mmu set 00090000, pos 00090000 [17:26:08]1162 mmu set 000a0000, pos 000a0000 [17:26:08]1162 mmu set 000b0000, pos 000b0000 [17:26:08]1162 mmu set 000c0000, pos 000c0000 [17:26:08]1162 mmu set 000d0000, pos 000d0000 [17:26:08]1162 mmu set 000e0000, pos 000e0000 [17:26:08]1162 mmu set 000f0000, pos 000f0000 [17:26:08]1162 mmu set 00100000, pos 00100000 [17:26:08]1162 mmu set 00110000, pos 00110000 [17:26:08]ets Jun 8 2016 00:22:57 [17:26:08] [17:26:08]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:08]configsip: 0, SPIWP:0xee [17:26:08]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:08]mode:QIO, clock div:1 [17:26:08]load:0x3fff0018,len:4 [17:26:08]load:0x928b2121,len:-1725455839 [17:26:08]1162 mmu set 00010000, pos 00010000 [17:26:08]1162 mmu set 00020000, pos 00020000 [17:26:08]1162 mmu set 00030000, pos 00030000 [17:26:08]1162 mmu set 00040000, pos 00040000 [17:26:08]1162 mmu set 00050000, pos 00050000 [17:26:08]1162 mmu set 00060000, pos 00060000 [17:26:08]1162 mmu set 00070000, pos 00070000 [17:26:08]1162 mmu set 00080000, pos 00080000 [17:26:08]1162 mmu set 00090000, pos 00090000 [17:26:08]1162 mmu set 000a0000, pos 000a0000 [17:26:08]1162 mmu set 000b0000, pos 000b0000 [17:26:08]1162 mmu set 000c0000, pos 000c0000 [17:26:08]1162 mmu set 000d0000, pos 000d0000 [17:26:08]1162 mmu set 000e0000, pos 000e0000 [17:26:08]1162 mmu set 000f0000, pos 000f0000 [17:26:08]1162 mmu set 00100000, pos 00100000 [17:26:08]1162 mmu set 00110000, pos 00110000 [17:26:08]ets Jun 8 2016 00:22:57 [17:26:08] [17:26:08]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:08]configsip: 0, SPIWP:0xee [17:26:08]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:08]mode:QIO, clock div:1 [17:26:08]load:0x3fff0018,len:4 [17:26:08]load:0x928b2121,len:-1725455839 [17:26:08]1162 mmu set 00010000, pos 00010000 [17:26:08]1162 mmu set 00020000, pos 00020000 [17:26:08]1162 mmu set 00030000, pos 00030000 [17:26:08]1162 mmu set 00040000, pos 00040000 [17:26:08]1162 mmu set 00050000, pos 00050000 [17:26:08]1162 mmu set 00060000, pos 00060000 [17:26:08]1162 mmu set 00070000, pos 00070000 [17:26:08]1162 mmu set 00080000, pos 00080000 [17:26:08]1162 mmu set 00090000, pos 00090000 [17:26:08]1162 mmu set 000a0000, pos 000a0000 [17:26:08]1162 mmu set 000b0000, pos 000b0000 [17:26:08]1162 mmu set 000c0000, pos 000c0000 [17:26:08]1162 mmu set 000d0000, pos 000d0000 [17:26:08]1162 mmu set 000e0000, pos 000e0000 [17:26:08]1162 mmu set 000f0000, pos 000f0000 [17:26:09]1162 mmu set 00100000, pos 00100000 [17:26:09]1162 mmu set 00110000, pos 00110000 [17:26:09]ets Jun 8 2016 00:22:57 [17:26:09] [17:26:09]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:09]configsip: 0, SPIWP:0xee [17:26:09]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:09]mode:QIO, clock div:1 [17:26:09]load:0x3fff0018,len:4 [17:26:09]load:0x928b2121,len:-1725455839 [17:26:09]1162 mmu set 00010000, pos 00010000 [17:26:09]1162 mmu set 00020000, pos 00020000 [17:26:09]1162 mmu set 00030000, pos 00030000 [17:26:09]1162 mmu set 00040000, pos 00040000 [17:26:09]1162 mmu set 00050000, pos 00050000 [17:26:09]1162 mmu set 00060000, pos 00060000 [17:26:09]1162 mmu set 00070000, pos 00070000 [17:26:09]1162 mmu set 00080000, pos 00080000 [17:26:09]1162 mmu set 00090000, pos 00090000 [17:26:09]1162 mmu set 000a0000, pos 000a0000 [17:26:09]1162 mmu set 000b0000, pos 000b0000 [17:26:09]1162 mmu set 000c0000, pos 000c0000 [17:26:09]1162 mmu set 000d0000, pos 000d0000 [17:26:09]1162 mmu set 000e0000, pos 000e0000 [17:26:09]1162 mmu set 000f0000, pos 000f0000 [17:26:09]1162 mmu set 00100000, pos 00100000 [17:26:09]1162 mmu set 00110000, pos 00110000 [17:26:09]ets Jun 8 2016 00:22:57 [17:26:09] [17:26:09]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:09]configsip: 0, SPIWP:0xee [17:26:09]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:09]mode:QIO, clock div:1 [17:26:09]load:0x3fff0018,len:4 [17:26:09]load:0x928b2121,len:-1725455839 [17:26:09]1162 mmu set 00010000, pos 00010000 [17:26:09]1162 mmu set 00020000, pos 00020000 [17:26:09]1162 mmu set 00030000, pos 00030000 [17:26:09]1162 mmu set 00040000, pos 00040000 [17:26:09]1162 mmu set 00050000, pos 00050000 [17:26:09]1162 mmu set 00060000, pos 00060000 [17:26:09]1162 mmu set 00070000, pos 00070000 [17:26:09]1162 mmu set 00080000, pos 00080000 [17:26:09]1162 mmu set 00090000, pos 00090000 [17:26:09]1162 mmu set 000a0000, pos 000a0000 [17:26:09]1162 mmu set 000b0000, pos 000b0000 [17:26:09]1162 mmu set 000c0000, pos 000c0000 [17:26:09]1162 mmu set 000d0000, pos 000d0000 [17:26:09]1162 mmu set 000e0000, pos 000e0000 [17:26:09]1162 mmu set 000f0000, pos 000f0000 [17:26:09]1162 mmu set 00100000, pos 00100000 [17:26:09]1162 mmu set 00110000, pos 00110000 [17:26:09]ets Jun 8 2016 00:22:57 [17:26:09] [17:26:09]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:09]configsip: 0, SPIWP:0xee [17:26:09]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:09]mode:QIO, clock div:1 [17:26:09]load:0x3fff0018,len:4 [17:26:09]load:0x928b2121,len:-1725455839 [17:26:09]1162 mmu set 00010000, pos 00010000 [17:26:09]1162 mmu set 00020000, pos 00020000 [17:26:09]1162 mmu set 00030000, pos 00030000 [17:26:09]1162 mmu set 00040000, pos 00040000 [17:26:09]1162 mmu set 00050000, pos 00050000 [17:26:09]1162 mmu set 00060000, pos 00060000 [17:26:09]1162 mmu set 00070000, pos 00070000 [17:26:09]1162 mmu set 00080000, pos 00080000 [17:26:09]1162 mmu set 00090000, pos 00090000 [17:26:10]1162 mmu set 000a0000, pos 000a0000 [17:26:10]1162 mmu set 000b0000, pos 000b0000 [17:26:10]1162 mmu set 000c0000, pos 000c0000 [17:26:10]1162 mmu set 000d0000, pos 000d0000 [17:26:10]1162 mmu set 000e0000, pos 000e0000 [17:26:10]1162 mmu set 000f0000, pos 000f0000 [17:26:10]1162 mmu set 00100000, pos 00100000 [17:26:10]1162 mmu set 00110000, pos 00110000 [17:26:10]ets Jun 8 2016 00:22:57 [17:26:10] [17:26:10]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:10]configsip: 0, SPIWP:0xee [17:26:10]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:10]mode:QIO, clock div:1 [17:26:10]load:0x3fff0018,len:4 [17:26:10]load:0x928b2121,len:-1725455839 [17:26:10]1162 mmu set 00010000, pos 00010000 [17:26:10]1162 mmu set 00020000, pos 00020000 [17:26:10]1162 mmu set 00030000, pos 00030000 [17:26:10]1162 mmu set 00040000, pos 00040000 [17:26:10]1162 mmu set 00050000, pos 00050000 [17:26:10]1162 mmu set 00060000, pos 00060000 [17:26:10]1162 mmu set 00070000, pos 00070000 [17:26:10]1162 mmu set 00080000, pos 00080000 [17:26:10]1162 mmu set 00090000, pos 00090000 [17:26:10]1162 mmu set 000a0000, pos 000a0000 [17:26:10]1162 mmu set 000b0000, pos 000b0000 [17:26:10]1162 mmu set 000c0000, pos 000c0000 [17:26:10]1162 mmu set 000d0000, pos 000d0000 [17:26:10]1162 mmu set 000e0000, pos 000e0000 [17:26:10]1162 mmu set 000f0000, pos 000f0000 [17:26:10]1162 mmu set 00100000, pos 00100000 [17:26:10]1162 mmu set 00110000, pos 00110000 [17:26:10]ets Jun 8 2016 00:22:57 [17:26:10] [17:26:10]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:10]configsip: 0, SPIWP:0xee [17:26:10]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:10]mode:QIO, clock div:1 [17:26:10]load:0x3fff0018,len:4 [17:26:10]load:0x928b2121,len:-1725455839 [17:26:10]1162 mmu set 00010000, pos 00010000 [17:26:10]1162 mmu set 00020000, pos 00020000 [17:26:10]1162 mmu set 00030000, pos 00030000 [17:26:10]1162 mmu set 00040000, pos 00040000 [17:26:10]1162 mmu set 00050000, pos 00050000 [17:26:10]1162 mmu set 00060000, pos 00060000 [17:26:10]1162 mmu set 00070000, pos 00070000 [17:26:10]1162 mmu set 00080000, pos 00080000 [17:26:10]1162 mmu set 00090000, pos 00090000 [17:26:10]1162 mmu set 000a0000, pos 000a0000 [17:26:10]1162 mmu set 000b0000, pos 000b0000 [17:26:10]1162 mmu set 000c0000, pos 000c0000 [17:26:10]1162 mmu set 000d0000, pos 000d0000 [17:26:10]1162 mmu set 000e0000, pos 000e0000 [17:26:10]1162 mmu set 000f0000, pos 000f0000 [17:26:10]1162 mmu set 00100000, pos 00100000 [17:26:10]1162 mmu set 00110000, pos 00110000 [17:26:10]ets Jun 8 2016 00:22:57 [17:26:10] [17:26:10]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:10]configsip: 0, SPIWP:0xee [17:26:10]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:10]mode:QIO, clock div:1 [17:26:10]load:0x3fff0018,len:4 [17:26:10]load:0x928b2121,len:-1725455839 [17:26:10]1162 mmu set 00010000, pos 00010000 [17:26:10]1162 mmu set 00020000, pos 00020000 [17:26:10]1162 mmu set 00030000, pos 00030000 [17:26:10]1162 mmu set 00040000, pos 00040000 [17:26:11]1162 mmu set 00050000, pos 00050000 [17:26:11]1162 mmu set 00060000, pos 00060000 [17:26:11]1162 mmu set 00070000, pos 00070000 [17:26:11]1162 mmu set 00080000, pos 00080000 [17:26:11]1162 mmu set 00090000, pos 00090000 [17:26:11]1162 mmu set 000a0000, pos 000a0000 [17:26:11]1162 mmu set 000b0000, pos 000b0000 [17:26:11]1162 mmu set 000c0000, pos 000c0000 [17:26:11]1162 mmu set 000d0000, pos 000d0000 [17:26:11]1162 mmu set 000e0000, pos 000e0000 [17:26:11]1162 mmu set 000f0000, pos 000f0000 [17:26:11]1162 mmu set 00100000, pos 00100000 [17:26:11]1162 mmu set 00110000, pos 00110000 [17:26:11]ets Jun 8 2016 00:22:57 [17:26:11] [17:26:11]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:11]configsip: 0, SPIWP:0xee [17:26:11]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:11]mode:QIO, clock div:1 [17:26:11]load:0x3fff0018,len:4 [17:26:11]load:0x928b2121,len:-1725455839 [17:26:11]1162 mmu set 00010000, pos 00010000 [17:26:11]1162 mmu set 00020000, pos 00020000 [17:26:11]1162 mmu set 00030000, pos 00030000 [17:26:11]1162 mmu set 00040000, pos 00040000 [17:26:11]1162 mmu set 00050000, pos 00050000 [17:26:11]1162 mmu set 00060000, pos 00060000 [17:26:11]1162 mmu set 00070000, pos 00070000 [17:26:11]1162 mmu set 00080000, pos 00080000 [17:26:11]1162 mmu set 00090000, pos 00090000 [17:26:11]1162 mmu set 000a0000, pos 000a0000 [17:26:11]1162 mmu set 000b0000, pos 000b0000 [17:26:11]1162 mmu set 000c0000, pos 000c0000 [17:26:11]1162 mmu set 000d0000, pos 000d0000 [17:26:11]1162 mmu set 000e0000, pos 000e0000 [17:26:11]1162 mmu set 000f0000, pos 000f0000 [17:26:11]1162 mmu set 00100000, pos 00100000 [17:26:11]1162 mmu set 00110000, pos 00110000 [17:26:11]ets Jun 8 2016 00:22:57 [17:26:11] [17:26:11]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:11]configsip: 0, SPIWP:0xee [17:26:11]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:11]mode:QIO, clock div:1 [17:26:11]load:0x3fff0018,len:4 [17:26:11]load:0x928b2121,len:-1725455839 [17:26:11]1162 mmu set 00010000, pos 00010000 [17:26:11]1162 mmu set 00020000, pos 00020000 [17:26:11]1162 mmu set 00030000, pos 00030000 [17:26:11]1162 mmu set 00040000, pos 00040000 [17:26:11]1162 mmu set 00050000, pos 00050000 [17:26:11]1162 mmu set 00060000, pos 00060000 [17:26:11]1162 mmu set 00070000, pos 00070000 [17:26:11]1162 mmu set 00080000, pos 00080000 [17:26:11]1162 mmu set 00090000, pos 00090000 [17:26:11]1162 mmu set 000a0000, pos 000a0000 [17:26:11]1162 mmu set 000b0000, pos 000b0000 [17:26:11]1162 mmu set 000c0000, pos 000c0000 [17:26:11]1162 mmu set 000d0000, pos 000d0000 [17:26:11]1162 mmu set 000e0000, pos 000e0000 [17:26:11]1162 mmu set 000f0000, pos 000f0000 [17:26:11]1162 mmu set 00100000, pos 00100000 [17:26:11]1162 mmu set 00110000, pos 00110000 [17:26:12]ets Jun 8 2016 00:22:57 [17:26:12] [17:26:12]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:12]configsip: 0, SPIWP:0xee [17:26:12]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:12]mode:QIO, clock div:1 [17:26:12]load:0x3fff0018,len:4 [17:26:12]load:0x928b2121,len:-1725455839 [17:26:12]1162 mmu set 00010000, pos 00010000 [17:26:12]1162 mmu set 00020000, pos 00020000 [17:26:12]1162 mmu set 00030000, pos 00030000 [17:26:12]1162 mmu set 00040000, pos 00040000 [17:26:12]1162 mmu set 00050000, pos 00050000 [17:26:12]1162 mmu set 00060000, pos 00060000 [17:26:12]1162 mmu set 00070000, pos 00070000 [17:26:12]1162 mmu set 00080000, pos 00080000 [17:26:12]1162 mmu set 00090000, pos 00090000 [17:26:12]1162 mmu set 000a0000, pos 000a0000 [17:26:12]1162 mmu set 000b0000, pos 000b0000 [17:26:12]1162 mmu set 000c0000, pos 000c0000 [17:26:12]1162 mmu set 000d0000, pos 000d0000 [17:26:12]1162 mmu set 000e0000, pos 000e0000 [17:26:12]1162 mmu set 000f0000, pos 000f0000 [17:26:12]1162 mmu set 00100000, pos 00100000 [17:26:12]1162 mmu set 00110000, pos 00110000 [17:26:12]ets Jun 8 2016 00:22:57 [17:26:12] [17:26:12]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:12]configsip: 0, SPIWP:0xee [17:26:12]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:12]mode:QIO, clock div:1 [17:26:12]load:0x3fff0018,len:4 [17:26:12]load:0x928b2121,len:-1725455839 [17:26:12]1162 mmu set 00010000, pos 00010000 [17:26:12]1162 mmu set 00020000, pos 00020000 [17:26:12]1162 mmu set 00030000, pos 00030000 [17:26:12]1162 mmu set 00040000, pos 00040000 [17:26:12]1162 mmu set 00050000, pos 00050000 [17:26:12]1162 mmu set 00060000, pos 00060000 [17:26:12]1162 mmu set 00070000, pos 00070000 [17:26:12]1162 mmu set 00080000, pos 00080000 [17:26:12]1162 mmu set 00090000, pos 00090000 [17:26:12]1162 mmu set 000a0000, pos 000a0000 [17:26:12]1162 mmu set 000b0000, pos 000b0000 [17:26:12]1162 mmu set 000c0000, pos 000c0000 [17:26:12]1162 mmu set 000d0000, pos 000d0000 [17:26:12]1162 mmu set 000e0000, pos 000e0000 [17:26:12]1162 mmu set 000f0000, pos 000f0000 [17:26:12]1162 mmu set 00100000, pos 00100000 [17:26:12]1162 mmu set 00110000, pos 00110000 [17:26:12]ets Jun 8 2016 00:22:57 [17:26:12] [17:26:12]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:12]configsip: 0, SPIWP:0xee [17:26:12]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:12]mode:QIO, clock div:1 [17:26:12]load:0x3fff0018,len:4 [17:26:12]load:0x928b2121,len:-1725455839 [17:26:12]1162 mmu set 00010000, pos 00010000 [17:26:12]1162 mmu set 00020000, pos 00020000 [17:26:12]1162 mmu set 00030000, pos 00030000 [17:26:12]1162 mmu set 00040000, pos 00040000 [17:26:12]1162 mmu set 00050000, pos 00050000 [17:26:12]1162 mmu set 00060000, pos 00060000 [17:26:12]1162 mmu set 00070000, pos 00070000 [17:26:12]1162 mmu set 00080000, pos 00080000 [17:26:12]1162 mmu set 00090000, pos 00090000 [17:26:12]1162 mmu set 000a0000, pos 000a0000 [17:26:12]1162 mmu set 000b0000, pos 000b0000 [17:26:12]1162 mmu set 000c0000, pos 000c0000 [17:26:13]1162 mmu set 000d0000, pos 000d0000 [17:26:13]1162 mmu set 000e0000, pos 000e0000 [17:26:13]1162 mmu set 000f0000, pos 000f0000 [17:26:13]1162 mmu set 00100000, pos 00100000 [17:26:13]1162 mmu set 00110000, pos 00110000 [17:26:13]ets Jun 8 2016 00:22:57 [17:26:13] [17:26:13]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:13]configsip: 0, SPIWP:0xee [17:26:13]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:13]mode:QIO, clock div:1 [17:26:13]load:0x3fff0018,len:4 [17:26:13]load:0x928b2121,len:-1725455839 [17:26:13]1162 mmu set 00010000, pos 00010000 [17:26:13]1162 mmu set 00020000, pos 00020000 [17:26:13]1162 mmu set 00030000, pos 00030000 [17:26:13]1162 mmu set 00040000, pos 00040000 [17:26:13]1162 mmu set 00050000, pos 00050000 [17:26:13]1162 mmu set 00060000, pos 00060000 [17:26:13]1162 mmu set 00070000, pos 00070000 [17:26:13]1162 mmu set 00080000, pos 00080000 [17:26:13]1162 mmu set 00090000, pos 00090000 [17:26:13]1162 mmu set 000a0000, pos 000a0000 [17:26:13]1162 mmu set 000b0000, pos 000b0000 [17:26:13]1162 mmu set 000c0000, pos 000c0000 [17:26:13]1162 mmu set 000d0000, pos 000d0000 [17:26:13]1162 mmu set 000e0000, pos 000e0000 [17:26:13]1162 mmu set 000f0000, pos 000f0000 [17:26:13]1162 mmu set 00100000, pos 00100000 [17:26:13]1162 mmu set 00110000, pos 00110000 [17:26:13]ets Jun 8 2016 00:22:57 [17:26:13] [17:26:13]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:13]configsip: 0, SPIWP:0xee [17:26:13]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:13]mode:QIO, clock div:1 [17:26:13]load:0x3fff0018,len:4 [17:26:13]load:0x928b2121,len:-1725455839 [17:26:13]1162 mmu set 00010000, pos 00010000 [17:26:13]1162 mmu set 00020000, pos 00020000 [17:26:13]1162 mmu set 00030000, pos 00030000 [17:26:13]1162 mmu set 00040000, pos 00040000 [17:26:13]1162 mmu set 00050000, pos 00050000 [17:26:13]1162 mmu set 00060000, pos 00060000 [17:26:13]1162 mmu set 00070000, pos 00070000 [17:26:13]1162 mmu set 00080000, pos 00080000 [17:26:13]1162 mmu set 00090000, pos 00090000 [17:26:13]1162 mmu set 000a0000, pos 000a0000 [17:26:13]1162 mmu set 000b0000, pos 000b0000 [17:26:13]1162 mmu set 000c0000, pos 000c0000 [17:26:13]1162 mmu set 000d0000, pos 000d0000 [17:26:13]1162 mmu set 000e0000, pos 000e0000 [17:26:13]1162 mmu set 000f0000, pos 000f0000 [17:26:13]1162 mmu set 00100000, pos 00100000 [17:26:13]1162 mmu set 00110000, pos 00110000 [17:26:13]ets Jun 8 2016 00:22:57 [17:26:13] [17:26:13]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:13]configsip: 0, SPIWP:0xee [17:26:13]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:13]mode:QIO, clock div:1 [17:26:13]load:0x3fff0018,len:4 [17:26:13]load:0x928b2121,len:-1725455839 [17:26:13]1162 mmu set 00010000, pos 00010000 [17:26:13]1162 mmu set 00020000, pos 00020000 [17:26:13]1162 mmu set 00030000, pos 00030000 [17:26:13]1162 mmu set 00040000, pos 00040000 [17:26:13]1162 mmu set 00050000, pos 00050000 [17:26:13]1162 mmu set 00060000, pos 00060000 [17:26:14]1162 mmu set 00070000, pos 00070000 [17:26:14]1162 mmu set 00080000, pos 00080000 [17:26:14]1162 mmu set 00090000, pos 00090000 [17:26:14]1162 mmu set 000a0000, pos 000a0000 [17:26:14]1162 mmu set 000b0000, pos 000b0000 [17:26:14]1162 mmu set 000c0000, pos 000c0000 [17:26:14]1162 mmu set 000d0000, pos 000d0000 [17:26:14]1162 mmu set 000e0000, pos 000e0000 [17:26:14]1162 mmu set 000f0000, pos 000f0000 [17:26:14]1162 mmu set 00100000, pos 00100000 [17:26:14]1162 mmu set 00110000, pos 00110000 [17:26:14]ets Jun 8 2016 00:22:57 [17:26:14] [17:26:14]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:14]configsip: 0, SPIWP:0xee [17:26:14]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:14]mode:QIO, clock div:1 [17:26:14]load:0x3fff0018,len:4 [17:26:14]load:0x928b2121,len:-1725455839 [17:26:14]1162 mmu set 00010000, pos 00010000 [17:26:14]1162 mmu set 00020000, pos 00020000 [17:26:14]1162 mmu set 00030000, pos 00030000 [17:26:14]1162 mmu set 00040000, pos 00040000 [17:26:14]1162 mmu set 00050000, pos 00050000 [17:26:14]1162 mmu set 00060000, pos 00060000 [17:26:14]1162 mmu set 00070000, pos 00070000 [17:26:14]1162 mmu set 00080000, pos 00080000 [17:26:14]1162 mmu set 00090000, pos 00090000 [17:26:14]1162 mmu set 000a0000, pos 000a0000 [17:26:14]1162 mmu set 000b0000, pos 000b0000 [17:26:14]1162 mmu set 000c0000, pos 000c0000 [17:26:14]1162 mmu set 000d0000, pos 000d0000 [17:26:14]1162 mmu set 000e0000, pos 000e0000 [17:26:14]1162 mmu set 000f0000, pos 000f0000 [17:26:14]1162 mmu set 00100000, pos 00100000 [17:26:14]1162 mmu set 00110000, pos 00110000 [17:26:14]ets Jun 8 2016 00:22:57 [17:26:14] [17:26:14]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:14]configsip: 0, SPIWP:0xee [17:26:14]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:14]mode:QIO, clock div:1 [17:26:14]load:0x3fff0018,len:4 [17:26:14]load:0x928b2121,len:-1725455839 [17:26:14]1162 mmu set 00010000, pos 00010000 [17:26:14]1162 mmu set 00020000, pos 00020000 [17:26:14]1162 mmu set 00030000, pos 00030000 [17:26:14]1162 mmu set 00040000, pos 00040000 [17:26:14]1162 mmu set 00050000, pos 00050000 [17:26:14]1162 mmu set 00060000, pos 00060000 [17:26:14]1162 mmu set 00070000, pos 00070000 [17:26:14]1162 mmu set 00080000, pos 00080000 [17:26:14]1162 mmu set 00090000, pos 00090000 [17:26:14]1162 mmu set 000a0000, pos 000a0000 [17:26:14]1162 mmu set 000b0000, pos 000b0000 [17:26:14]1162 mmu set 000c0000, pos 000c0000 [17:26:14]1162 mmu set 000d0000, pos 000d0000 [17:26:14]1162 mmu set 000e0000, pos 000e0000 [17:26:14]1162 mmu set 000f0000, pos 000f0000 [17:26:14]1162 mmu set 00100000, pos 00100000 [17:26:14]1162 mmu set 00110000, pos 00110000 [17:26:14]ets Jun 8 2016 00:22:57 [17:26:14] [17:26:14]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:14]configsip: 0, SPIWP:0xee [17:26:14]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:14]mode:QIO, clock div:1 [17:26:14]load:0x3fff0018,len:4 [17:26:14]load:0x928b2121,len:-1725455839 [17:26:14]1162 mmu set 00010000, pos 00010000 [17:26:15]1162 mmu set 00020000, pos 00020000 [17:26:15]1162 mmu set 00030000, pos 00030000 [17:26:15]1162 mmu set 00040000, pos 00040000 [17:26:15]1162 mmu set 00050000, pos 00050000 [17:26:15]1162 mmu set 00060000, pos 00060000 [17:26:15]1162 mmu set 00070000, pos 00070000 [17:26:15]1162 mmu set 00080000, pos 00080000 [17:26:15]1162 mmu set 00090000, pos 00090000 [17:26:15]1162 mmu set 000a0000, pos 000a0000 [17:26:15]1162 mmu set 000b0000, pos 000b0000 [17:26:15]1162 mmu set 000c0000, pos 000c0000 [17:26:15]1162 mmu set 000d0000, pos 000d0000 [17:26:15]1162 mmu set 000e0000, pos 000e0000 [17:26:15]1162 mmu set 000f0000, pos 000f0000 [17:26:15]1162 mmu set 00100000, pos 00100000 [17:26:15]1162 mmu set 00110000, pos 00110000 [17:26:15]ets Jun 8 2016 00:22:57 [17:26:15] [17:26:15]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:15]configsip: 0, SPIWP:0xee [17:26:15]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:15]mode:QIO, clock div:1 [17:26:15]load:0x3fff0018,len:4 [17:26:15]load:0x928b2121,len:-1725455839 [17:26:15]1162 mmu set 00010000, pos 00010000 [17:26:15]1162 mmu set 00020000, pos 00020000 [17:26:15]1162 mmu set 00030000, pos 00030000 [17:26:15]1162 mmu set 00040000, pos 00040000 [17:26:15]1162 mmu set 00050000, pos 00050000 [17:26:15]1162 mmu set 00060000, pos 00060000 [17:26:15]1162 mmu set 00070000, pos 00070000 [17:26:15]1162 mmu set 00080000, pos 00080000 [17:26:15]1162 mmu set 00090000, pos 00090000 [17:26:15]1162 mmu set 000a0000, pos 000a0000 [17:26:15]1162 mmu set 000b0000, pos 000b0000 [17:26:15]1162 mmu set 000c0000, pos 000c0000 [17:26:15]1162 mmu set 000d0000, pos 000d0000 [17:26:15]1162 mmu set 000e0000, pos 000e0000 [17:26:15]1162 mmu set 000f0000, pos 000f0000 [17:26:15]1162 mmu set 00100000, pos 00100000 [17:26:15]1162 mmu set 00110000, pos 00110000 [17:26:15]ets Jun 8 2016 00:22:57 [17:26:15] [17:26:15]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:15]configsip: 0, SPIWP:0xee [17:26:15]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:15]mode:QIO, clock div:1 [17:26:15]load:0x3fff0018,len:4 [17:26:15]load:0x928b2121,len:-1725455839 [17:26:15]1162 mmu set 00010000, pos 00010000 [17:26:15]1162 mmu set 00020000, pos 00020000 [17:26:15]1162 mmu set 00030000, pos 00030000 [17:26:15]1162 mmu set 00040000, pos 00040000 [17:26:15]1162 mmu set 00050000, pos 00050000 [17:26:15]1162 mmu set 00060000, pos 00060000 [17:26:15]1162 mmu set 00070000, pos 00070000 [17:26:15]1162 mmu set 00080000, pos 00080000 [17:26:15]1162 mmu set 00090000, pos 00090000 [17:26:15]1162 mmu set 000a0000, pos 000a0000 [17:26:15]1162 mmu set 000b0000, pos 000b0000 [17:26:15]1162 mmu set 000c0000, pos 000c0000 [17:26:15]1162 mmu set 000d0000, pos 000d0000 [17:26:15]1162 mmu set 000e0000, pos 000e0000 [17:26:16]1162 mmu set 000f0000, pos 000f0000 [17:26:16]1162 mmu set 00100000, pos 00100000 [17:26:16]1162 mmu set 00110000, pos 00110000 [17:26:16]ets Jun 8 2016 00:22:57 [17:26:16] [17:26:16]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:16]configsip: 0, SPIWP:0xee [17:26:16]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:16]mode:QIO, clock div:1 [17:26:16]load:0x3fff0018,len:4 [17:26:16]load:0x928b2121,len:-1725455839 [17:26:16]1162 mmu set 00010000, pos 00010000 [17:26:16]1162 mmu set 00020000, pos 00020000 [17:26:16]1162 mmu set 00030000, pos 00030000 [17:26:16]1162 mmu set 00040000, pos 00040000 [17:26:16]1162 mmu set 00050000, pos 00050000 [17:26:16]1162 mmu set 00060000, pos 00060000 [17:26:16]1162 mmu set 00070000, pos 00070000 [17:26:16]1162 mmu set 00080000, pos 00080000 [17:26:16]1162 mmu set 00090000, pos 00090000 [17:26:16]1162 mmu set 000a0000, pos 000a0000 [17:26:16]1162 mmu set 000b0000, pos 000b0000 [17:26:16]1162 mmu set 000c0000, pos 000c0000 [17:26:16]1162 mmu set 000d0000, pos 000d0000 [17:26:16]1162 mmu set 000e0000, pos 000e0000 [17:26:16]1162 mmu set 000f0000, pos 000f0000 [17:26:16]1162 mmu set 00100000, pos 00100000 [17:26:16]1162 mmu set 00110000, pos 00110000 [17:26:16]ets Jun 8 2016 00:22:57 [17:26:16] [17:26:16]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:16]configsip: 0, SPIWP:0xee [17:26:16]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:16]mode:QIO, clock div:1 [17:26:16]load:0x3fff0018,len:4 [17:26:16]load:0x928b2121,len:-1725455839 [17:26:16]1162 mmu set 00010000, pos 00010000 [17:26:16]1162 mmu set 00020000, pos 00020000 [17:26:16]1162 mmu set 00030000, pos 00030000 [17:26:16]1162 mmu set 00040000, pos 00040000 [17:26:16]1162 mmu set 00050000, pos 00050000 [17:26:16]1162 mmu set 00060000, pos 00060000 [17:26:16]1162 mmu set 00070000, pos 00070000 [17:26:16]1162 mmu set 00080000, pos 00080000 [17:26:16]1162 mmu set 00090000, pos 00090000 [17:26:16]1162 mmu set 000a0000, pos 000a0000 [17:26:16]1162 mmu set 000b0000, pos 000b0000 [17:26:16]1162 mmu set 000c0000, pos 000c0000 [17:26:16]1162 mmu set 000d0000, pos 000d0000 [17:26:16]1162 mmu set 000e0000, pos 000e0000 [17:26:16]1162 mmu set 000f0000, pos 000f0000 [17:26:16]1162 mmu set 00100000, pos 00100000 [17:26:16]1162 mmu set 00110000, pos 00110000 [17:26:16]ets Jun 8 2016 00:22:57 [17:26:16] [17:26:16]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:16]configsip: 0, SPIWP:0xee [17:26:16]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:16]mode:QIO, clock div:1 [17:26:16]load:0x3fff0018,len:4 [17:26:16]load:0x928b2121,len:-1725455839 [17:26:16]1162 mmu set 00010000, pos 00010000 [17:26:16]1162 mmu set 00020000, pos 00020000 [17:26:16]1162 mmu set 00030000, pos 00030000 [17:26:16]1162 mmu set 00040000, pos 00040000 [17:26:16]1162 mmu set 00050000, pos 00050000 [17:26:16]1162 mmu set 00060000, pos 00060000 [17:26:16]1162 mmu set 00070000, pos 00070000 [17:26:16]1162 mmu set 00080000, pos 00080000 [17:26:16]1162 mmu set 00090000, pos 00090000 [17:26:17]1162 mmu set 000a0000, pos 000a0000 [17:26:17]1162 mmu set 000b0000, pos 000b0000 [17:26:17]1162 mmu set 000c0000, pos 000c0000 [17:26:17]1162 mmu set 000d0000, pos 000d0000 [17:26:17]1162 mmu set 000e0000, pos 000e0000 [17:26:17]1162 mmu set 000f0000, pos 000f0000 [17:26:17]1162 mmu set 00100000, pos 00100000 [17:26:17]1162 mmu set 00110000, pos 00110000 [17:26:17]ets Jun 8 2016 00:22:57 [17:26:17] [17:26:17]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:17]configsip: 0, SPIWP:0xee [17:26:17]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:17]mode:QIO, clock div:1 [17:26:17]load:0x3fff0018,len:4 [17:26:17]load:0x928b2121,len:-1725455839 [17:26:17]1162 mmu set 00010000, pos 00010000 [17:26:17]1162 mmu set 00020000, pos 00020000 [17:26:17]1162 mmu set 00030000, pos 00030000 [17:26:17]1162 mmu set 00040000, pos 00040000 [17:26:17]1162 mmu set 00050000, pos 00050000 [17:26:17]1162 mmu set 00060000, pos 00060000 [17:26:17]1162 mmu set 00070000, pos 00070000 [17:26:17]1162 mmu set 00080000, pos 00080000 [17:26:17]1162 mmu set 00090000, pos 00090000 [17:26:17]1162 mmu set 000a0000, pos 000a0000 [17:26:17]1162 mmu set 000b0000, pos 000b0000 [17:26:17]1162 mmu set 000c0000, pos 000c0000 [17:26:17]1162 mmu set 000d0000, pos 000d0000 [17:26:17]1162 mmu set 000e0000, pos 000e0000 [17:26:17]1162 mmu set 000f0000, pos 000f0000 [17:26:17]1162 mmu set 00100000, pos 00100000 [17:26:17]1162 mmu set 00110000, pos 00110000 [17:26:17]ets Jun 8 2016 00:22:57 [17:26:17] [17:26:17]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:17]configsip: 0, SPIWP:0xee [17:26:17]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:17]mode:QIO, clock div:1 [17:26:17]load:0x3fff0018,len:4 [17:26:17]load:0x928b2121,len:-1725455839 [17:26:17]1162 mmu set 00010000, pos 00010000 [17:26:17]1162 mmu set 00020000, pos 00020000 [17:26:17]1162 mmu set 00030000, pos 00030000 [17:26:17]1162 mmu set 00040000, pos 00040000 [17:26:17]1162 mmu set 00050000, pos 00050000 [17:26:17]1162 mmu set 00060000, pos 00060000 [17:26:17]1162 mmu set 00070000, pos 00070000 [17:26:17]1162 mmu set 00080000, pos 00080000 [17:26:17]1162 mmu set 00090000, pos 00090000 [17:26:17]1162 mmu set 000a0000, pos 000a0000 [17:26:17]1162 mmu set 000b0000, pos 000b0000 [17:26:17]1162 mmu set 000c0000, pos 000c0000 [17:26:17]1162 mmu set 000d0000, pos 000d0000 [17:26:17]1162 mmu set 000e0000, pos 000e0000 [17:26:17]1162 mmu set 000f0000, pos 000f0000 [17:26:17]1162 mmu set 00100000, pos 00100000 [17:26:17]1162 mmu set 00110000, pos 00110000 [17:26:17]ets Jun 8 2016 00:22:57 [17:26:17] [17:26:17]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:17]configsip: 0, SPIWP:0xee [17:26:17]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:17]mode:QIO, clock div:1 [17:26:17]load:0x3fff0018,len:4 [17:26:17]load:0x928b2121,len:-1725455839 [17:26:17]1162 mmu set 00010000, pos 00010000 [17:26:17]1162 mmu set 00020000, pos 00020000 [17:26:17]1162 mmu set 00030000, pos 00030000 [17:26:18]1162 mmu set 00040000, pos 00040000 [17:26:18]1162 mmu set 00050000, pos 00050000 [17:26:18]1162 mmu set 00060000, pos 00060000 [17:26:18]1162 mmu set 00070000, pos 00070000 [17:26:18]1162 mmu set 00080000, pos 00080000 [17:26:18]1162 mmu set 00090000, pos 00090000 [17:26:18]1162 mmu set 000a0000, pos 000a0000 [17:26:18]1162 mmu set 000b0000, pos 000b0000 [17:26:18]1162 mmu set 000c0000, pos 000c0000 [17:26:18]1162 mmu set 000d0000, pos 000d0000 [17:26:18]1162 mmu set 000e0000, pos 000e0000 [17:26:18]1162 mmu set 000f0000, pos 000f0000 [17:26:18]1162 mmu set 00100000, pos 00100000 [17:26:18]1162 mmu set 00110000, pos 00110000 [17:26:18]ets Jun 8 2016 00:22:57 [17:26:18] [17:26:18]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:18]configsip: 0, SPIWP:0xee [17:26:18]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:18]mode:QIO, clock div:1 [17:26:18]load:0x3fff0018,len:4 [17:26:18]load:0x928b2121,len:-1725455839 [17:26:18]1162 mmu set 00010000, pos 00010000 [17:26:18]1162 mmu set 00020000, pos 00020000 [17:26:18]1162 mmu set 00030000, pos 00030000 [17:26:18]1162 mmu set 00040000, pos 00040000 [17:26:18]1162 mmu set 00050000, pos 00050000 [17:26:18]1162 mmu set 00060000, pos 00060000 [17:26:18]1162 mmu set 00070000, pos 00070000 [17:26:18]1162 mmu set 00080000, pos 00080000 [17:26:18]1162 mmu set 00090000, pos 00090000 [17:26:18]1162 mmu set 000a0000, pos 000a0000 [17:26:18]1162 mmu set 000b0000, pos 000b0000 [17:26:18]1162 mmu set 000c0000, pos 000c0000 [17:26:18]1162 mmu set 000d0000, pos 000d0000 [17:26:18]1162 mmu set 000e0000, pos 000e0000 [17:26:18]1162 mmu set 000f0000, pos 000f0000 [17:26:18]1162 mmu set 00100000, pos 00100000 [17:26:18]1162 mmu set 00110000, pos 00110000 [17:26:18]ets Jun 8 2016 00:22:57 [17:26:18] [17:26:18]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:18]configsip: 0, SPIWP:0xee [17:26:18]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:18]mode:QIO, clock div:1 [17:26:18]load:0x3fff0018,len:4 [17:26:18]load:0x928b2121,len:-1725455839 [17:26:18]1162 mmu set 00010000, pos 00010000 [17:26:18]1162 mmu set 00020000, pos 00020000 [17:26:18]1162 mmu set 00030000, pos 00030000 [17:26:18]1162 mmu set 00040000, pos 00040000 [17:26:18]1162 mmu set 00050000, pos 00050000 [17:26:18]1162 mmu set 00060000, pos 00060000 [17:26:18]1162 mmu set 00070000, pos 00070000 [17:26:18]1162 mmu set 00080000, pos 00080000 [17:26:18]1162 mmu set 00090000, pos 00090000 [17:26:18]1162 mmu set 000a0000, pos 000a0000 [17:26:18]1162 mmu set 000b0000, pos 000b0000 [17:26:18]1162 mmu set 000c0000, pos 000c0000 [17:26:18]1162 mmu set 000d0000, pos 000d0000 [17:26:18]1162 mmu set 000e0000, pos 000e0000 [17:26:18]1162 mmu set 000f0000, pos 000f0000 [17:26:18]1162 mmu set 00100000, pos 00100000 [17:26:19]1162 mmu set 00110000, pos 00110000 [17:26:19]ets Jun 8 2016 00:22:57 [17:26:19] [17:26:19]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:19]configsip: 0, SPIWP:0xee [17:26:19]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:19]mode:QIO, clock div:1 [17:26:19]load:0x3fff0018,len:4 [17:26:19]load:0x928b2121,len:-1725455839 [17:26:19]1162 mmu set 00010000, pos 00010000 [17:26:19]1162 mmu set 00020000, pos 00020000 [17:26:19]1162 mmu set 00030000, pos 00030000 [17:26:19]1162 mmu set 00040000, pos 00040000 [17:26:19]1162 mmu set 00050000, pos 00050000 [17:26:19]1162 mmu set 00060000, pos 00060000 [17:26:19]1162 mmu set 00070000, pos 00070000 [17:26:19]1162 mmu set 00080000, pos 00080000 [17:26:19]1162 mmu set 00090000, pos 00090000 [17:26:19]1162 mmu set 000a0000, pos 000a0000 [17:26:19]1162 mmu set 000b0000, pos 000b0000 [17:26:19]1162 mmu set 000c0000, pos 000c0000 [17:26:19]1162 mmu set 000d0000, pos 000d0000 [17:26:19]1162 mmu set 000e0000, pos 000e0000 [17:26:19]1162 mmu set 000f0000, pos 000f0000 [17:26:19]1162 mmu set 00100000, pos 00100000 [17:26:19]1162 mmu set 00110000, pos 00110000 [17:26:19]ets Jun 8 2016 00:22:57 [17:26:19] [17:26:19]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:19]configsip: 0, SPIWP:0xee [17:26:19]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:19]mode:QIO, clock div:1 [17:26:19]load:0x3fff0018,len:4 [17:26:19]load:0x928b2121,len:-1725455839 [17:26:19]1162 mmu set 00010000, pos 00010000 [17:26:19]1162 mmu set 00020000, pos 00020000 [17:26:19]1162 mmu set 00030000, pos 00030000 [17:26:19]1162 mmu set 00040000, pos 00040000 [17:26:19]1162 mmu set 00050000, pos 00050000 [17:26:19]1162 mmu set 00060000, pos 00060000 [17:26:19]1162 mmu set 00070000, pos 00070000 [17:26:19]1162 mmu set 00080000, pos 00080000 [17:26:19]1162 mmu set 00090000, pos 00090000 [17:26:19]1162 mmu set 000a0000, pos 000a0000 [17:26:19]1162 mmu set 000b0000, pos 000b0000 [17:26:19]1162 mmu set 000c0000, pos 000c0000 [17:26:19]1162 mmu set 000d0000, pos 000d0000 [17:26:19]1162 mmu set 000e0000, pos 000e0000 [17:26:19]1162 mmu set 000f0000, pos 000f0000 [17:26:19]1162 mmu set 00100000, pos 00100000 [17:26:19]1162 mmu set 00110000, pos 00110000 [17:26:19]ets Jun 8 2016 00:22:57 [17:26:19] [17:26:19]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:19]configsip: 0, SPIWP:0xee [17:26:19]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:19]mode:QIO, clock div:1 [17:26:19]load:0x3fff0018,len:4 [17:26:19]load:0x928b2121,len:-1725455839 [17:26:19]1162 mmu set 00010000, pos 00010000 [17:26:19]1162 mmu set 00020000, pos 00020000 [17:26:19]1162 mmu set 00030000, pos 00030000 [17:26:19]1162 mmu set 00040000, pos 00040000 [17:26:19]1162 mmu set 00050000, pos 00050000 [17:26:19]1162 mmu set 00060000, pos 00060000 [17:26:19]1162 mmu set 00070000, pos 00070000 [17:26:19]1162 mmu set 00080000, pos 00080000 [17:26:19]1162 mmu set 00090000, pos 00090000 [17:26:19]1162 mmu set 000a0000, pos 000a0000 [17:26:19]1162 mmu set 000b0000, pos 000b0000 [17:26:20]1162 mmu set 000c0000, pos 000c0000 [17:26:20]1162 mmu set 000d0000, pos 000d0000 [17:26:20]1162 mmu set 000e0000, pos 000e0000 [17:26:20]1162 mmu set 000f0000, pos 000f0000 [17:26:20]1162 mmu set 00100000, pos 00100000 [17:26:20]1162 mmu set 00110000, pos 00110000 [17:26:20]ets Jun 8 2016 00:22:57 [17:26:20] [17:26:20]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:20]configsip: 0, SPIWP:0xee [17:26:20]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:20]mode:QIO, clock div:1 [17:26:20]load:0x3fff0018,len:4 [17:26:20]load:0x928b2121,len:-1725455839 [17:26:20]1162 mmu set 00010000, pos 00010000 [17:26:20]1162 mmu set 00020000, pos 00020000 [17:26:20]1162 mmu set 00030000, pos 00030000 [17:26:20]1162 mmu set 00040000, pos 00040000 [17:26:20]1162 mmu set 00050000, pos 00050000 [17:26:20]1162 mmu set 00060000, pos 00060000 [17:26:20]1162 mmu set 00070000, pos 00070000 [17:26:20]1162 mmu set 00080000, pos 00080000 [17:26:20]1162 mmu set 00090000, pos 00090000 [17:26:20]1162 mmu set 000a0000, pos 000a0000 [17:26:20]1162 mmu set 000b0000, pos 000b0000 [17:26:20]1162 mmu set 000c0000, pos 000c0000 [17:26:20]1162 mmu set 000d0000, pos 000d0000 [17:26:20]1162 mmu set 000e0000, pos 000e0000 [17:26:20]1162 mmu set 000f0000, pos 000f0000 [17:26:20]1162 mmu set 00100000, pos 00100000 [17:26:20]1162 mmu set 00110000, pos 00110000 [17:26:20]ets Jun 8 2016 00:22:57 [17:26:20] [17:26:20]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:20]configsip: 0, SPIWP:0xee [17:26:20]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:20]mode:QIO, clock div:1 [17:26:20]load:0x3fff0018,len:4 [17:26:20]load:0x928b2121,len:-1725455839 [17:26:20]1162 mmu set 00010000, pos 00010000 [17:26:20]1162 mmu set 00020000, pos 00020000 [17:26:20]1162 mmu set 00030000, pos 00030000 [17:26:20]1162 mmu set 00040000, pos 00040000 [17:26:20]1162 mmu set 00050000, pos 00050000 [17:26:20]1162 mmu set 00060000, pos 00060000 [17:26:20]1162 mmu set 00070000, pos 00070000 [17:26:20]1162 mmu set 00080000, pos 00080000 [17:26:20]1162 mmu set 00090000, pos 00090000 [17:26:20]1162 mmu set 000a0000, pos 000a0000 [17:26:20]1162 mmu set 000b0000, pos 000b0000 [17:26:20]1162 mmu set 000c0000, pos 000c0000 [17:26:20]1162 mmu set 000d0000, pos 000d0000 [17:26:20]1162 mmu set 000e0000, pos 000e0000 [17:26:20]1162 mmu set 000f0000, pos 000f0000 [17:26:20]1162 mmu set 00100000, pos 00100000 [17:26:20]1162 mmu set 00110000, pos 00110000 [17:26:20]ets Jun 8 2016 00:22:57 [17:26:20] [17:26:20]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:20]configsip: 0, SPIWP:0xee [17:26:20]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:20]mode:QIO, clock div:1 [17:26:20]load:0x3fff0018,len:4 [17:26:20]load:0x928b2121,len:-1725455839 [17:26:20]1162 mmu set 00010000, pos 00010000 [17:26:20]1162 mmu set 00020000, pos 00020000 [17:26:20]1162 mmu set 00030000, pos 00030000 [17:26:20]1162 mmu set 00040000, pos 00040000 [17:26:20]1162 mmu set 00050000, pos 00050000 [17:26:20]1162 mmu set 00060000, pos 00060000 [17:26:21]1162 mmu set 00070000, pos 00070000 [17:26:21]1162 mmu set 00080000, pos 00080000 [17:26:21]1162 mmu set 00090000, pos 00090000 [17:26:21]1162 mmu set 000a0000, pos 000a0000 [17:26:21]1162 mmu set 000b0000, pos 000b0000 [17:26:21]1162 mmu set 000c0000, pos 000c0000 [17:26:21]1162 mmu set 000d0000, pos 000d0000 [17:26:21]1162 mmu set 000e0000, pos 000e0000 [17:26:21]1162 mmu set 000f0000, pos 000f0000 [17:26:21]1162 mmu set 00100000, pos 00100000 [17:26:21]1162 mmu set 00110000, pos 00110000 [17:26:21]ets Jun 8 2016 00:22:57 [17:26:21] [17:26:21]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:21]configsip: 0, SPIWP:0xee [17:26:21]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:21]mode:QIO, clock div:1 [17:26:21]load:0x3fff0018,len:4 [17:26:21]load:0x928b2121,len:-1725455839 [17:26:21]1162 mmu set 00010000, pos 00010000 [17:26:21]1162 mmu set 00020000, pos 00020000 [17:26:21]1162 mmu set 00030000, pos 00030000 [17:26:21]1162 mmu set 00040000, pos 00040000 [17:26:21]1162 mmu set 00050000, pos 00050000 [17:26:21]1162 mmu set 00060000, pos 00060000 [17:26:21]1162 mmu set 00070000, pos 00070000 [17:26:21]1162 mmu set 00080000, pos 00080000 [17:26:21]1162 mmu set 00090000, pos 00090000 [17:26:21]1162 mmu set 000a0000, pos 000a0000 [17:26:21]1162 mmu set 000b0000, pos 000b0000 [17:26:21]1162 mmu set 000c0000, pos 000c0000 [17:26:21]1162 mmu set 000d0000, pos 000d0000 [17:26:21]1162 mmu set 000e0000, pos 000e0000 [17:26:21]1162 mmu set 000f0000, pos 000f0000 [17:26:21]1162 mmu set 00100000, pos 00100000 [17:26:21]1162 mmu set 00110000, pos 00110000 [17:26:21]ets Jun 8 2016 00:22:57 [17:26:21] [17:26:21]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:21]configsip: 0, SPIWP:0xee [17:26:21]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:21]mode:QIO, clock div:1 [17:26:21]load:0x3fff0018,len:4 [17:26:21]load:0x928b2121,len:-1725455839 [17:26:21]1162 mmu set 00010000, pos 00010000 [17:26:21]1162 mmu set 00020000, pos 00020000 [17:26:21]1162 mmu set 00030000, pos 00030000 [17:26:21]1162 mmu set 00040000, pos 00040000 [17:26:21]1162 mmu set 00050000, pos 00050000 [17:26:21]1162 mmu set 00060000, pos 00060000 [17:26:21]1162 mmu set 00070000, pos 00070000 [17:26:21]1162 mmu set 00080000, pos 00080000 [17:26:21]1162 mmu set 00090000, pos 00090000 [17:26:21]1162 mmu set 000a0000, pos 000a0000 [17:26:21]1162 mmu set 000b0000, pos 000b0000 [17:26:21]1162 mmu set 000c0000, pos 000c0000 [17:26:21]1162 mmu set 000d0000, pos 000d0000 [17:26:21]1162 mmu set 000e0000, pos 000e0000 [17:26:21]1162 mmu set 000f0000, pos 000f0000 [17:26:21]1162 mmu set 00100000, pos 00100000 [17:26:21]1162 mmu set 00110000, pos 00110000 [17:26:21]ets Jun 8 2016 00:22:57 [17:26:21] [17:26:21]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:21]configsip: 0, SPIWP:0xee [17:26:21]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:21]mode:QIO, clock div:1 [17:26:21]load:0x3fff0018,len:4 [17:26:21]load:0x928b2121,len:-1725455839 [17:26:21]1162 mmu set 00010000, pos 00010000 [17:26:22]1162 mmu set 00020000, pos 00020000 [17:26:22]1162 mmu set 00030000, pos 00030000 [17:26:22]1162 mmu set 00040000, pos 00040000 [17:26:22]1162 mmu set 00050000, pos 00050000 [17:26:22]1162 mmu set 00060000, pos 00060000 [17:26:22]1162 mmu set 00070000, pos 00070000 [17:26:22]1162 mmu set 00080000, pos 00080000 [17:26:22]1162 mmu set 00090000, pos 00090000 [17:26:22]1162 mmu set 000a0000, pos 000a0000 [17:26:22]1162 mmu set 000b0000, pos 000b0000 [17:26:22]1162 mmu set 000c0000, pos 000c0000 [17:26:22]1162 mmu set 000d0000, pos 000d0000 [17:26:22]1162 mmu set 000e0000, pos 000e0000 [17:26:22]1162 mmu set 000f0000, pos 000f0000 [17:26:22]1162 mmu set 00100000, pos 00100000 [17:26:22]1162 mmu set 00110000, pos 00110000 [17:26:22]ets Jun 8 2016 00:22:57 [17:26:22] [17:26:22]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:22]configsip: 0, SPIWP:0xee [17:26:22]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:22]mode:QIO, clock div:1 [17:26:22]load:0x3fff0018,len:4 [17:26:22]load:0x928b2121,len:-1725455839 [17:26:22]1162 mmu set 00010000, pos 00010000 [17:26:22]1162 mmu set 00020000, pos 00020000 [17:26:22]1162 mmu set 00030000, pos 00030000 [17:26:22]1162 mmu set 00040000, pos 00040000 [17:26:22]1162 mmu set 00050000, pos 00050000 [17:26:22]1162 mmu set 00060000, pos 00060000 [17:26:22]1162 mmu set 00070000, pos 00070000 [17:26:22]1162 mmu set 00080000, pos 00080000 [17:26:22]1162 mmu set 00090000, pos 00090000 [17:26:22]1162 mmu set 000a0000, pos 000a0000 [17:26:22]1162 mmu set 000b0000, pos 000b0000 [17:26:22]1162 mmu set 000c0000, pos 000c0000 [17:26:22]1162 mmu set 000d0000, pos 000d0000 [17:26:22]1162 mmu set 000e0000, pos 000e0000 [17:26:22]1162 mmu set 000f0000, pos 000f0000 [17:26:22]1162 mmu set 00100000, pos 00100000 [17:26:22]1162 mmu set 00110000, pos 00110000 [17:26:22]ets Jun 8 2016 00:22:57 [17:26:22] [17:26:22]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:22]configsip: 0, SPIWP:0xee [17:26:22]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:22]mode:QIO, clock div:1 [17:26:22]load:0x3fff0018,len:4 [17:26:22]load:0x928b2121,len:-1725455839 [17:26:22]1162 mmu set 00010000, pos 00010000 [17:26:22]1162 mmu set 00020000, pos 00020000 [17:26:22]1162 mmu set 00030000, pos 00030000 [17:26:22]1162 mmu set 00040000, pos 00040000 [17:26:22]1162 mmu set 00050000, pos 00050000 [17:26:22]1162 mmu set 00060000, pos 00060000 [17:26:22]1162 mmu set 00070000, pos 00070000 [17:26:22]1162 mmu set 00080000, pos 00080000 [17:26:22]1162 mmu set 00090000, pos 00090000 [17:26:22]1162 mmu set 000a0000, pos 000a0000 [17:26:22]1162 mmu set 000b0000, pos 000b0000 [17:26:22]1162 mmu set 000c0000, pos 000c0000 [17:26:22]1162 mmu set 000d0000, pos 000d0000 [17:26:23]1162 mmu set 000e0000, pos 000e0000 [17:26:23]1162 mmu set 000f0000, pos 000f0000 [17:26:23]1162 mmu set 00100000, pos 00100000 [17:26:23]1162 mmu set 00110000, pos 00110000 [17:26:23]ets Jun 8 2016 00:22:57 [17:26:23] [17:26:23]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:23]configsip: 0, SPIWP:0xee [17:26:23]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:23]mode:QIO, clock div:1 [17:26:23]load:0x3fff0018,len:4 [17:26:23]load:0x928b2121,len:-1725455839 [17:26:23]1162 mmu set 00010000, pos 00010000 [17:26:23]1162 mmu set 00020000, pos 00020000 [17:26:23]1162 mmu set 00030000, pos 00030000 [17:26:23]1162 mmu set 00040000, pos 00040000 [17:26:23]1162 mmu set 00050000, pos 00050000 [17:26:23]1162 mmu set 00060000, pos 00060000 [17:26:23]1162 mmu set 00070000, pos 00070000 [17:26:23]1162 mmu set 00080000, pos 00080000 [17:26:23]1162 mmu set 00090000, pos 00090000 [17:26:23]1162 mmu set 000a0000, pos 000a0000 [17:26:23]1162 mmu set 000b0000, pos 000b0000 [17:26:23]1162 mmu set 000c0000, pos 000c0000 [17:26:23]1162 mmu set 000d0000, pos 000d0000 [17:26:23]1162 mmu set 000e0000, pos 000e0000 [17:26:23]1162 mmu set 000f0000, pos 000f0000 [17:26:23]1162 mmu set 00100000, pos 00100000 [17:26:23]1162 mmu set 00110000, pos 00110000 [17:26:23]ets Jun 8 2016 00:22:57 [17:26:23] [17:26:23]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:23]configsip: 0, SPIWP:0xee [17:26:23]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:23]mode:QIO, clock div:1 [17:26:23]load:0x3fff0018,len:4 [17:26:23]load:0x928b2121,len:-1725455839 [17:26:23]1162 mmu set 00010000, pos 00010000 [17:26:23]1162 mmu set 00020000, pos 00020000 [17:26:23]1162 mmu set 00030000, pos 00030000 [17:26:23]1162 mmu set 00040000, pos 00040000 [17:26:23]1162 mmu set 00050000, pos 00050000 [17:26:23]1162 mmu set 00060000, pos 00060000 [17:26:23]1162 mmu set 00070000, pos 00070000 [17:26:23]1162 mmu set 00080000, pos 00080000 [17:26:23]1162 mmu set 00090000, pos 00090000 [17:26:23]1162 mmu set 000a0000, pos 000a0000 [17:26:23]1162 mmu set 000b0000, pos 000b0000 [17:26:23]1162 mmu set 000c0000, pos 000c0000 [17:26:23]1162 mmu set 000d0000, pos 000d0000 [17:26:23]1162 mmu set 000e0000, pos 000e0000 [17:26:23]1162 mmu set 000f0000, pos 000f0000 [17:26:23]1162 mmu set 00100000, pos 00100000 [17:26:23]1162 mmu set 00110000, pos 00110000 [17:26:23]ets Jun 8 2016 00:22:57 [17:26:23] [17:26:23]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:23]configsip: 0, SPIWP:0xee [17:26:23]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:23]mode:QIO, clock div:1 [17:26:23]load:0x3fff0018,len:4 [17:26:23]load:0x928b2121,len:-1725455839 [17:26:23]1162 mmu set 00010000, pos 00010000 [17:26:23]1162 mmu set 00020000, pos 00020000 [17:26:23]1162 mmu set 00030000, pos 00030000 [17:26:23]1162 mmu set 00040000, pos 00040000 [17:26:23]1162 mmu set 00050000, pos 00050000 [17:26:23]1162 mmu set 00060000, pos 00060000 [17:26:23]1162 mmu set 00070000, pos 00070000 [17:26:23]1162 mmu set 00080000, pos 00080000 [17:26:24]1162 mmu set 00090000, pos 00090000 [17:26:24]1162 mmu set 000a0000, pos 000a0000 [17:26:24]1162 mmu set 000b0000, pos 000b0000 [17:26:24]1162 mmu set 000c0000, pos 000c0000 [17:26:24]1162 mmu set 000d0000, pos 000d0000 [17:26:24]1162 mmu set 000e0000, pos 000e0000 [17:26:24]1162 mmu set 000f0000, pos 000f0000 [17:26:24]1162 mmu set 00100000, pos 00100000 [17:26:24]1162 mmu set 00110000, pos 00110000 [17:26:24]ets Jun 8 2016 00:22:57 [17:26:24] [17:26:24]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:24]configsip: 0, SPIWP:0xee [17:26:24]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:24]mode:QIO, clock div:1 [17:26:24]load:0x3fff0018,len:4 [17:26:24]load:0x928b2121,len:-1725455839 [17:26:24]1162 mmu set 00010000, pos 00010000 [17:26:24]1162 mmu set 00020000, pos 00020000 [17:26:24]1162 mmu set 00030000, pos 00030000 [17:26:24]1162 mmu set 00040000, pos 00040000 [17:26:24]1162 mmu set 00050000, pos 00050000 [17:26:24]1162 mmu set 00060000, pos 00060000 [17:26:24]1162 mmu set 00070000, pos 00070000 [17:26:24]1162 mmu set 00080000, pos 00080000 [17:26:24]1162 mmu set 00090000, pos 00090000 [17:26:24]1162 mmu set 000a0000, pos 000a0000 [17:26:24]1162 mmu set 000b0000, pos 000b0000 [17:26:24]1162 mmu set 000c0000, pos 000c0000 [17:26:24]1162 mmu set 000d0000, pos 000d0000 [17:26:24]1162 mmu set 000e0000, pos 000e0000 [17:26:24]1162 mmu set 000f0000, pos 000f0000 [17:26:24]1162 mmu set 00100000, pos 00100000 [17:26:24]1162 mmu set 00110000, pos 00110000 [17:26:24]ets Jun 8 2016 00:22:57 [17:26:24] [17:26:24]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:24]configsip: 0, SPIWP:0xee [17:26:24]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:24]mode:QIO, clock div:1 [17:26:24]load:0x3fff0018,len:4 [17:26:24]load:0x928b2121,len:-1725455839 [17:26:24]1162 mmu set 00010000, pos 00010000 [17:26:24]1162 mmu set 00020000, pos 00020000 [17:26:24]1162 mmu set 00030000, pos 00030000 [17:26:24]1162 mmu set 00040000, pos 00040000 [17:26:24]1162 mmu set 00050000, pos 00050000 [17:26:24]1162 mmu set 00060000, pos 00060000 [17:26:24]1162 mmu set 00070000, pos 00070000 [17:26:24]1162 mmu set 00080000, pos 00080000 [17:26:24]1162 mmu set 00090000, pos 00090000 [17:26:24]1162 mmu set 000a0000, pos 000a0000 [17:26:24]1162 mmu set 000b0000, pos 000b0000 [17:26:24]1162 mmu set 000c0000, pos 000c0000 [17:26:24]1162 mmu set 000d0000, pos 000d0000 [17:26:24]1162 mmu set 000e0000, pos 000e0000 [17:26:24]1162 mmu set 000f0000, pos 000f0000 [17:26:24]1162 mmu set 00100000, pos 00100000 [17:26:24]1162 mmu set 00110000, pos 00110000 [17:26:24]ets Jun 8 2016 00:22:57 [17:26:24] [17:26:24]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:24]configsip: 0, SPIWP:0xee [17:26:24]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:24]mode:QIO, clock div:1 [17:26:24]load:0x3fff0018,len:4 [17:26:24]load:0x928b2121,len:-1725455839 [17:26:24]1162 mmu set 00010000, pos 00010000 [17:26:24]1162 mmu set 00020000, pos 00020000 [17:26:24]1162 mmu set 00030000, pos 00030000 [17:26:25]1162 mmu set 00040000, pos 00040000 [17:26:25]1162 mmu set 00050000, pos 00050000 [17:26:25]1162 mmu set 00060000, pos 00060000 [17:26:25]1162 mmu set 00070000, pos 00070000 [17:26:25]1162 mmu set 00080000, pos 00080000 [17:26:25]1162 mmu set 00090000, pos 00090000 [17:26:25]1162 mmu set 000a0000, pos 000a0000 [17:26:25]1162 mmu set 000b0000, pos 000b0000 [17:26:25]1162 mmu set 000c0000, pos 000c0000 [17:26:25]1162 mmu set 000d0000, pos 000d0000 [17:26:25]1162 mmu set 000e0000, pos 000e0000 [17:26:25]1162 mmu set 000f0000, pos 000f0000 [17:26:25]1162 mmu set 00100000, pos 00100000 [17:26:25]1162 mmu set 00110000, pos 00110000 [17:26:25]ets Jun 8 2016 00:22:57 [17:26:25] [17:26:25]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:25]configsip: 0, SPIWP:0xee [17:26:25]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:25]mode:QIO, clock div:1 [17:26:25]load:0x3fff0018,len:4 [17:26:25]load:0x928b2121,len:-1725455839 [17:26:25]1162 mmu set 00010000, pos 00010000 [17:26:25]1162 mmu set 00020000, pos 00020000 [17:26:25]1162 mmu set 00030000, pos 00030000 [17:26:25]1162 mmu set 00040000, pos 00040000 [17:26:25]1162 mmu set 00050000, pos 00050000 [17:26:25]1162 mmu set 00060000, pos 00060000 [17:26:25]1162 mmu set 00070000, pos 00070000 [17:26:25]1162 mmu set 00080000, pos 00080000 [17:26:25]1162 mmu set 00090000, pos 00090000 [17:26:25]1162 mmu set 000a0000, pos 000a0000 [17:26:25]1162 mmu set 000b0000, pos 000b0000 [17:26:25]1162 mmu set 000c0000, pos 000c0000 [17:26:25]1162 mmu set 000d0000, pos 000d0000 [17:26:25]1162 mmu set 000e0000, pos 000e0000 [17:26:25]1162 mmu set 000f0000, pos 000f0000 [17:26:25]1162 mmu set 00100000, pos 00100000 [17:26:25]1162 mmu set 00110000, pos 00110000 [17:26:25]ets Jun 8 2016 00:22:57 [17:26:25] [17:26:25]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:25]configsip: 0, SPIWP:0xee [17:26:25]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:25]mode:QIO, clock div:1 [17:26:25]load:0x3fff0018,len:4 [17:26:25]load:0x928b2121,len:-1725455839 [17:26:25]1162 mmu set 00010000, pos 00010000 [17:26:25]1162 mmu set 00020000, pos 00020000 [17:26:25]1162 mmu set 00030000, pos 00030000 [17:26:25]1162 mmu set 00040000, pos 00040000 [17:26:25]1162 mmu set 00050000, pos 00050000 [17:26:25]1162 mmu set 00060000, pos 00060000 [17:26:25]1162 mmu set 00070000, pos 00070000 [17:26:25]1162 mmu set 00080000, pos 00080000 [17:26:25]1162 mmu set 00090000, pos 00090000 [17:26:25]1162 mmu set 000a0000, pos 000a0000 [17:26:25]1162 mmu set 000b0000, pos 000b0000 [17:26:25]1162 mmu set 000c0000, pos 000c0000 [17:26:25]1162 mmu set 000d0000, pos 000d0000 [17:26:25]1162 mmu set 000e0000, pos 000e0000 [17:26:25]1162 mmu set 000f0000, pos 000f0000 [17:26:25]1162 mmu set 00100000, pos 00100000 [17:26:26]1162 mmu set 00110000, pos 00110000 [17:26:26]ets Jun 8 2016 00:22:57 [17:26:26] [17:26:26]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:26]configsip: 0, SPIWP:0xee [17:26:26]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:26]mode:QIO, clock div:1 [17:26:26]load:0x3fff0018,len:4 [17:26:26]load:0x928b2121,len:-1725455839 [17:26:26]1162 mmu set 00010000, pos 00010000 [17:26:26]1162 mmu set 00020000, pos 00020000 [17:26:26]1162 mmu set 00030000, pos 00030000 [17:26:26]1162 mmu set 00040000, pos 00040000 [17:26:26]1162 mmu set 00050000, pos 00050000 [17:26:26]1162 mmu set 00060000, pos 00060000 [17:26:26]1162 mmu set 00070000, pos 00070000 [17:26:26]1162 mmu set 00080000, pos 00080000 [17:26:26]1162 mmu set 00090000, pos 00090000 [17:26:26]1162 mmu set 000a0000, pos 000a0000 [17:26:26]1162 mmu set 000b0000, pos 000b0000 [17:26:26]1162 mmu set 000c0000, pos 000c0000 [17:26:26]1162 mmu set 000d0000, pos 000d0000 [17:26:26]1162 mmu set 000e0000, pos 000e0000 [17:26:26]1162 mmu set 000f0000, pos 000f0000 [17:26:26]1162 mmu set 00100000, pos 00100000 [17:26:26]1162 mmu set 00110000, pos 00110000 [17:26:26]ets Jun 8 2016 00:22:57 [17:26:26] [17:26:26]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:26]configsip: 0, SPIWP:0xee [17:26:26]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:26]mode:QIO, clock div:1 [17:26:26]load:0x3fff0018,len:4 [17:26:26]load:0x928b2121,len:-1725455839 [17:26:26]1162 mmu set 00010000, pos 00010000 [17:26:26]1162 mmu set 00020000, pos 00020000 [17:26:26]1162 mmu set 00030000, pos 00030000 [17:26:26]1162 mmu set 00040000, pos 00040000 [17:26:26]1162 mmu set 00050000, pos 00050000 [17:26:26]1162 mmu set 00060000, pos 00060000 [17:26:26]1162 mmu set 00070000, pos 00070000 [17:26:26]1162 mmu set 00080000, pos 00080000 [17:26:26]1162 mmu set 00090000, pos 00090000 [17:26:26]1162 mmu set 000a0000, pos 000a0000 [17:26:26]1162 mmu set 000b0000, pos 000b0000 [17:26:26]1162 mmu set 000c0000, pos 000c0000 [17:26:26]1162 mmu set 000d0000, pos 000d0000 [17:26:26]1162 mmu set 000e0000, pos 000e0000 [17:26:26]1162 mmu set 000f0000, pos 000f0000 [17:26:26]1162 mmu set 00100000, pos 00100000 [17:26:26]1162 mmu set 00110000, pos 00110000 [17:26:26]ets Jun 8 2016 00:22:57 [17:26:26] [17:26:26]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:26]configsip: 0, SPIWP:0xee [17:26:26]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:26]mode:QIO, clock div:1 [17:26:26]load:0x3fff0018,len:4 [17:26:26]load:0x928b2121,len:-1725455839 [17:26:26]1162 mmu set 00010000, pos 00010000 [17:26:26]1162 mmu set 00020000, pos 00020000 [17:26:26]1162 mmu set 00030000, pos 00030000 [17:26:26]1162 mmu set 00040000, pos 00040000 [17:26:26]1162 mmu set 00050000, pos 00050000 [17:26:26]1162 mmu set 00060000, pos 00060000 [17:26:26]1162 mmu set 00070000, pos 00070000 [17:26:26]1162 mmu set 00080000, pos 00080000 [17:26:26]1162 mmu set 00090000, pos 00090000 [17:26:26]1162 mmu set 000a0000, pos 000a0000 [17:26:27]1162 mmu set 000b0000, pos 000b0000 [17:26:27]1162 mmu set 000c0000, pos 000c0000 [17:26:27]1162 mmu set 000d0000, pos 000d0000 [17:26:27]1162 mmu set 000e0000, pos 000e0000 [17:26:27]1162 mmu set 000f0000, pos 000f0000 [17:26:27]1162 mmu set 00100000, pos 00100000 [17:26:27]1162 mmu set 00110000, pos 00110000 [17:26:27]ets Jun 8 2016 00:22:57 [17:26:27] [17:26:27]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:27]configsip: 0, SPIWP:0xee [17:26:27]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:27]mode:QIO, clock div:1 [17:26:27]load:0x3fff0018,len:4 [17:26:27]load:0x928b2121,len:-1725455839 [17:26:27]1162 mmu set 00010000, pos 00010000 [17:26:27]1162 mmu set 00020000, pos 00020000 [17:26:27]1162 mmu set 00030000, pos 00030000 [17:26:27]1162 mmu set 00040000, pos 00040000 [17:26:27]1162 mmu set 00050000, pos 00050000 [17:26:27]1162 mmu set 00060000, pos 00060000 [17:26:27]1162 mmu set 00070000, pos 00070000 [17:26:27]1162 mmu set 00080000, pos 00080000 [17:26:27]1162 mmu set 00090000, pos 00090000 [17:26:27]1162 mmu set 000a0000, pos 000a0000 [17:26:27]1162 mmu set 000b0000, pos 000b0000 [17:26:27]1162 mmu set 000c0000, pos 000c0000 [17:26:27]1162 mmu set 000d0000, pos 000d0000 [17:26:27]1162 mmu set 000e0000, pos 000e0000 [17:26:27]1162 mmu set 000f0000, pos 000f0000 [17:26:27]1162 mmu set 00100000, pos 00100000 [17:26:27]1162 mmu set 00110000, pos 00110000 [17:26:27]ets Jun 8 2016 00:22:57 [17:26:27] [17:26:27]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:27]configsip: 0, SPIWP:0xee [17:26:27]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:27]mode:QIO, clock div:1 [17:26:27]load:0x3fff0018,len:4 [17:26:27]load:0x928b2121,len:-1725455839 [17:26:27]1162 mmu set 00010000, pos 00010000 [17:26:27]1162 mmu set 00020000, pos 00020000 [17:26:27]1162 mmu set 00030000, pos 00030000 [17:26:27]1162 mmu set 00040000, pos 00040000 [17:26:27]1162 mmu set 00050000, pos 00050000 [17:26:27]1162 mmu set 00060000, pos 00060000 [17:26:27]1162 mmu set 00070000, pos 00070000 [17:26:27]1162 mmu set 00080000, pos 00080000 [17:26:27]1162 mmu set 00090000, pos 00090000 [17:26:27]1162 mmu set 000a0000, pos 000a0000 [17:26:27]1162 mmu set 000b0000, pos 000b0000 [17:26:27]1162 mmu set 000c0000, pos 000c0000 [17:26:27]1162 mmu set 000d0000, pos 000d0000 [17:26:27]1162 mmu set 000e0000, pos 000e0000 [17:26:27]1162 mmu set 000f0000, pos 000f0000 [17:26:27]1162 mmu set 00100000, pos 00100000 [17:26:27]1162 mmu set 00110000, pos 00110000 [17:26:27]ets Jun 8 2016 00:22:57 [17:26:27] [17:26:27]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:27]configsip: 0, SPIWP:0xee [17:26:27]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:27]mode:QIO, clock div:1 [17:26:27]load:0x3fff0018,len:4 [17:26:27]load:0x928b2121,len:-1725455839 [17:26:27]1162 mmu set 00010000, pos 00010000 [17:26:27]1162 mmu set 00020000, pos 00020000 [17:26:27]1162 mmu set 00030000, pos 00030000 [17:26:27]1162 mmu set 00040000, pos 00040000 [17:26:27]1162 mmu set 00050000, pos 00050000 [17:26:28]1162 mmu set 00060000, pos 00060000 [17:26:28]1162 mmu set 00070000, pos 00070000 [17:26:28]1162 mmu set 00080000, pos 00080000 [17:26:28]1162 mmu set 00090000, pos 00090000 [17:26:28]1162 mmu set 000a0000, pos 000a0000 [17:26:28]1162 mmu set 000b0000, pos 000b0000 [17:26:28]1162 mmu set 000c0000, pos 000c0000 [17:26:28]1162 mmu set 000d0000, pos 000d0000 [17:26:28]1162 mmu set 000e0000, pos 000e0000 [17:26:28]1162 mmu set 000f0000, pos 000f0000 [17:26:28]1162 mmu set 00100000, pos 00100000 [17:26:28]1162 mmu set 00110000, pos 00110000 [17:26:28]ets Jun 8 2016 00:22:57 [17:26:28] [17:26:28]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:28]configsip: 0, SPIWP:0xee [17:26:28]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:28]mode:QIO, clock div:1 [17:26:28]load:0x3fff0018,len:4 [17:26:28]load:0x928b2121,len:-1725455839 [17:26:28]1162 mmu set 00010000, pos 00010000 [17:26:28]1162 mmu set 00020000, pos 00020000 [17:26:28]1162 mmu set 00030000, pos 00030000 [17:26:28]1162 mmu set 00040000, pos 00040000 [17:26:28]1162 mmu set 00050000, pos 00050000 [17:26:28]1162 mmu set 00060000, pos 00060000 [17:26:28]1162 mmu set 00070000, pos 00070000 [17:26:28]1162 mmu set 00080000, pos 00080000 [17:26:28]1162 mmu set 00090000, pos 00090000 [17:26:28]1162 mmu set 000a0000, pos 000a0000 [17:26:28]1162 mmu set 000b0000, pos 000b0000 [17:26:28]1162 mmu set 000c0000, pos 000c0000 [17:26:28]1162 mmu set 000d0000, pos 000d0000 [17:26:28]1162 mmu set 000e0000, pos 000e0000 [17:26:28]1162 mmu set 000f0000, pos 000f0000 [17:26:28]1162 mmu set 00100000, pos 00100000 [17:26:28]1162 mmu set 00110000, pos 00110000 [17:26:28]ets Jun 8 2016 00:22:57 [17:26:28] [17:26:28]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:28]configsip: 0, SPIWP:0xee [17:26:28]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:28]mode:QIO, clock div:1 [17:26:28]load:0x3fff0018,len:4 [17:26:28]load:0x928b2121,len:-1725455839 [17:26:28]1162 mmu set 00010000, pos 00010000 [17:26:28]1162 mmu set 00020000, pos 00020000 [17:26:28]1162 mmu set 00030000, pos 00030000 [17:26:28]1162 mmu set 00040000, pos 00040000 [17:26:28]1162 mmu set 00050000, pos 00050000 [17:26:28]1162 mmu set 00060000, pos 00060000 [17:26:28]1162 mmu set 00070000, pos 00070000 [17:26:28]1162 mmu set 00080000, pos 00080000 [17:26:28]1162 mmu set 00090000, pos 00090000 [17:26:28]1162 mmu set 000a0000, pos 000a0000 [17:26:28]1162 mmu set 000b0000, pos 000b0000 [17:26:28]1162 mmu set 000c0000, pos 000c0000 [17:26:28]1162 mmu set 000d0000, pos 000d0000 [17:26:28]1162 mmu set 000e0000, pos 000e0000 [17:26:28]1162 mmu set 000f0000, pos 000f0000 [17:26:28]1162 mmu set 00100000, pos 00100000 [17:26:28]1162 mmu set 00110000, pos 00110000 [17:26:28]ets Jun 8 2016 00:22:57 [17:26:28] [17:26:28]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:28]configsip: 0, SPIWP:0xee [17:26:28]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:28]mode:QIO, clock div:1 [17:26:28]load:0x3fff0018,len:4 [17:26:29]load:0x928b2121,len:-1725455839 [17:26:29]1162 mmu set 00010000, pos 00010000 [17:26:29]1162 mmu set 00020000, pos 00020000 [17:26:29]1162 mmu set 00030000, pos 00030000 [17:26:29]1162 mmu set 00040000, pos 00040000 [17:26:29]1162 mmu set 00050000, pos 00050000 [17:26:29]1162 mmu set 00060000, pos 00060000 [17:26:29]1162 mmu set 00070000, pos 00070000 [17:26:29]1162 mmu set 00080000, pos 00080000 [17:26:29]1162 mmu set 00090000, pos 00090000 [17:26:29]1162 mmu set 000a0000, pos 000a0000 [17:26:29]1162 mmu set 000b0000, pos 000b0000 [17:26:29]1162 mmu set 000c0000, pos 000c0000 [17:26:29]1162 mmu set 000d0000, pos 000d0000 [17:26:29]1162 mmu set 000e0000, pos 000e0000 [17:26:29]1162 mmu set 000f0000, pos 000f0000 [17:26:29]1162 mmu set 00100000, pos 00100000 [17:26:29]1162 mmu set 00110000, pos 00110000 [17:26:29]ets Jun 8 2016 00:22:57 [17:26:29] [17:26:29]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:29]configsip: 0, SPIWP:0xee [17:26:29]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:29]mode:QIO, clock div:1 [17:26:29]load:0x3fff0018,len:4 [17:26:29]load:0x928b2121,len:-1725455839 [17:26:29]1162 mmu set 00010000, pos 00010000 [17:26:29]1162 mmu set 00020000, pos 00020000 [17:26:29]1162 mmu set 00030000, pos 00030000 [17:26:29]1162 mmu set 00040000, pos 00040000 [17:26:29]1162 mmu set 00050000, pos 00050000 [17:26:29]1162 mmu set 00060000, pos 00060000 [17:26:29]1162 mmu set 00070000, pos 00070000 [17:26:29]1162 mmu set 00080000, pos 00080000 [17:26:29]1162 mmu set 00090000, pos 00090000 [17:26:29]1162 mmu set 000a0000, pos 000a0000 [17:26:29]1162 mmu set 000b0000, pos 000b0000 [17:26:29]1162 mmu set 000c0000, pos 000c0000 [17:26:29]1162 mmu set 000d0000, pos 000d0000 [17:26:29]1162 mmu set 000e0000, pos 000e0000 [17:26:29]1162 mmu set 000f0000, pos 000f0000 [17:26:29]1162 mmu set 00100000, pos 00100000 [17:26:29]1162 mmu set 00110000, pos 00110000 [17:26:29]ets Jun 8 2016 00:22:57 [17:26:29] [17:26:29]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:29]configsip: 0, SPIWP:0xee [17:26:29]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:29]mode:QIO, clock div:1 [17:26:29]load:0x3fff0018,len:4 [17:26:29]load:0x928b2121,len:-1725455839 [17:26:29]1162 mmu set 00010000, pos 00010000 [17:26:29]1162 mmu set 00020000, pos 00020000 [17:26:29]1162 mmu set 00030000, pos 00030000 [17:26:29]1162 mmu set 00040000, pos 00040000 [17:26:29]1162 mmu set 00050000, pos 00050000 [17:26:29]1162 mmu set 00060000, pos 00060000 [17:26:29]1162 mmu set 00070000, pos 00070000 [17:26:29]1162 mmu set 00080000, pos 00080000 [17:26:29]1162 mmu set 00090000, pos 00090000 [17:26:29]1162 mmu set 000a0000, pos 000a0000 [17:26:29]1162 mmu set 000b0000, pos 000b0000 [17:26:29]1162 mmu set 000c0000, pos 000c0000 [17:26:29]1162 mmu set 000d0000, pos 000d0000 [17:26:30]1162 mmu set 000e0000, pos 000e0000 [17:26:30]1162 mmu set 000f0000, pos 000f0000 [17:26:30]1162 mmu set 00100000, pos 00100000 [17:26:30]1162 mmu set 00110000, pos 00110000 [17:26:30]ets Jun 8 2016 00:22:57 [17:26:30] [17:26:30]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:30]configsip: 0, SPIWP:0xee [17:26:30]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:30]mode:QIO, clock div:1 [17:26:30]load:0x3fff0018,len:4 [17:26:30]load:0x928b2121,len:-1725455839 [17:26:30]1162 mmu set 00010000, pos 00010000 [17:26:30]1162 mmu set 00020000, pos 00020000 [17:26:30]1162 mmu set 00030000, pos 00030000 [17:26:30]1162 mmu set 00040000, pos 00040000 [17:26:30]1162 mmu set 00050000, pos 00050000 [17:26:30]1162 mmu set 00060000, pos 00060000 [17:26:30]1162 mmu set 00070000, pos 00070000 [17:26:30]1162 mmu set 00080000, pos 00080000 [17:26:30]1162 mmu set 00090000, pos 00090000 [17:26:30]1162 mmu set 000a0000, pos 000a0000 [17:26:30]1162 mmu set 000b0000, pos 000b0000 [17:26:30]1162 mmu set 000c0000, pos 000c0000 [17:26:30]1162 mmu set 000d0000, pos 000d0000 [17:26:30]1162 mmu set 000e0000, pos 000e0000 [17:26:30]1162 mmu set 000f0000, pos 000f0000 [17:26:30]1162 mmu set 00100000, pos 00100000 [17:26:30]1162 mmu set 00110000, pos 00110000 [17:26:30]ets Jun 8 2016 00:22:57 [17:26:30] [17:26:30]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:30]configsip: 0, SPIWP:0xee [17:26:30]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:30]mode:QIO, clock div:1 [17:26:30]load:0x3fff0018,len:4 [17:26:30]load:0x928b2121,len:-1725455839 [17:26:30]1162 mmu set 00010000, pos 00010000 [17:26:30]1162 mmu set 00020000, pos 00020000 [17:26:30]1162 mmu set 00030000, pos 00030000 [17:26:30]1162 mmu set 00040000, pos 00040000 [17:26:30]1162 mmu set 00050000, pos 00050000 [17:26:30]1162 mmu set 00060000, pos 00060000 [17:26:30]1162 mmu set 00070000, pos 00070000 [17:26:30]1162 mmu set 00080000, pos 00080000 [17:26:30]1162 mmu set 00090000, pos 00090000 [17:26:30]1162 mmu set 000a0000, pos 000a0000 [17:26:30]1162 mmu set 000b0000, pos 000b0000 [17:26:30]1162 mmu set 000c0000, pos 000c0000 [17:26:30]1162 mmu set 000d0000, pos 000d0000 [17:26:30]1162 mmu set 000e0000, pos 000e0000 [17:26:30]1162 mmu set 000f0000, pos 000f0000 [17:26:30]1162 mmu set 00100000, pos 00100000 [17:26:30]1162 mmu set 00110000, pos 00110000 [17:26:30]ets Jun 8 2016 00:22:57 [17:26:30] [17:26:30]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:30]configsip: 0, SPIWP:0xee [17:26:30]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:30]mode:QIO, clock div:1 [17:26:30]load:0x3fff0018,len:4 [17:26:30]load:0x928b2121,len:-1725455839 [17:26:30]1162 mmu set 00010000, pos 00010000 [17:26:30]1162 mmu set 00020000, pos 00020000 [17:26:30]1162 mmu set 00030000, pos 00030000 [17:26:30]1162 mmu set 00040000, pos 00040000 [17:26:30]1162 mmu set 00050000, pos 00050000 [17:26:30]1162 mmu set 00060000, pos 00060000 [17:26:30]1162 mmu set 00070000, pos 00070000 [17:26:30]1162 mmu set 00080000, pos 00080000 [17:26:31]1162 mmu set 00090000, pos 00090000 [17:26:31]1162 mmu set 000a0000, pos 000a0000 [17:26:31]1162 mmu set 000b0000, pos 000b0000 [17:26:31]1162 mmu set 000c0000, pos 000c0000 [17:26:31]1162 mmu set 000d0000, pos 000d0000 [17:26:31]1162 mmu set 000e0000, pos 000e0000 [17:26:31]1162 mmu set 000f0000, pos 000f0000 [17:26:31]1162 mmu set 00100000, pos 00100000 [17:26:31]1162 mmu set 00110000, pos 00110000 [17:26:31]ets Jun 8 2016 00:22:57 [17:26:31] [17:26:31]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:31]configsip: 0, SPIWP:0xee [17:26:31]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:31]mode:QIO, clock div:1 [17:26:31]load:0x3fff0018,len:4 [17:26:31]load:0x928b2121,len:-1725455839 [17:26:31]1162 mmu set 00010000, pos 00010000 [17:26:31]1162 mmu set 00020000, pos 00020000 [17:26:31]1162 mmu set 00030000, pos 00030000 [17:26:31]1162 mmu set 00040000, pos 00040000 [17:26:31]1162 mmu set 00050000, pos 00050000 [17:26:31]1162 mmu set 00060000, pos 00060000 [17:26:31]1162 mmu set 00070000, pos 00070000 [17:26:31]1162 mmu set 00080000, pos 00080000 [17:26:31]1162 mmu set 00090000, pos 00090000 [17:26:31]1162 mmu set 000a0000, pos 000a0000 [17:26:31]1162 mmu set 000b0000, pos 000b0000 [17:26:31]1162 mmu set 000c0000, pos 000c0000 [17:26:31]1162 mmu set 000d0000, pos 000d0000 [17:26:31]1162 mmu set 000e0000, pos 000e0000 [17:26:31]1162 mmu set 000f0000, pos 000f0000 [17:26:31]1162 mmu set 00100000, pos 00100000 [17:26:31]1162 mmu set 00110000, pos 00110000 [17:26:31]ets Jun 8 2016 00:22:57 [17:26:31] [17:26:31]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:31]configsip: 0, SPIWP:0xee [17:26:31]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:31]mode:QIO, clock div:1 [17:26:31]load:0x3fff0018,len:4 [17:26:31]load:0x928b2121,len:-1725455839 [17:26:31]1162 mmu set 00010000, pos 00010000 [17:26:31]1162 mmu set 00020000, pos 00020000 [17:26:31]1162 mmu set 00030000, pos 00030000 [17:26:31]1162 mmu set 00040000, pos 00040000 [17:26:31]1162 mmu set 00050000, pos 00050000 [17:26:31]1162 mmu set 00060000, pos 00060000 [17:26:31]1162 mmu set 00070000, pos 00070000 [17:26:31]1162 mmu set 00080000, pos 00080000 [17:26:31]1162 mmu set 00090000, pos 00090000 [17:26:31]1162 mmu set 000a0000, pos 000a0000 [17:26:31]1162 mmu set 000b0000, pos 000b0000 [17:26:31]1162 mmu set 000c0000, pos 000c0000 [17:26:31]1162 mmu set 000d0000, pos 000d0000 [17:26:31]1162 mmu set 000e0000, pos 000e0000 [17:26:31]1162 mmu set 000f0000, pos 000f0000 [17:26:31]1162 mmu set 00100000, pos 00100000 [17:26:31]1162 mmu set 00110000, pos 00110000 [17:26:31]ets Jun 8 2016 00:22:57 [17:26:31] [17:26:31]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:31]configsip: 0, SPIWP:0xee [17:26:31]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:31]mode:QIO, clock div:1 [17:26:31]load:0x3fff0018,len:4 [17:26:31]load:0x928b2121,len:-1725455839 [17:26:31]1162 mmu set 00010000, pos 00010000 [17:26:31]1162 mmu set 00020000, pos 00020000 [17:26:32]1162 mmu set 00030000, pos 00030000 [17:26:32]1162 mmu set 00040000, pos 00040000 [17:26:32]1162 mmu set 00050000, pos 00050000 [17:26:32]1162 mmu set 00060000, pos 00060000 [17:26:32]1162 mmu set 00070000, pos 00070000 [17:26:32]1162 mmu set 00080000, pos 00080000 [17:26:32]1162 mmu set 00090000, pos 00090000 [17:26:32]1162 mmu set 000a0000, pos 000a0000 [17:26:32]1162 mmu set 000b0000, pos 000b0000 [17:26:32]1162 mmu set 000c0000, pos 000c0000 [17:26:32]1162 mmu set 000d0000, pos 000d0000 [17:26:32]1162 mmu set 000e0000, pos 000e0000 [17:26:32]1162 mmu set 000f0000, pos 000f0000 [17:26:32]1162 mmu set 00100000, pos 00100000 [17:26:32]1162 mmu set 00110000, pos 00110000 [17:26:32]ets Jun 8 2016 00:22:57 [17:26:32] [17:26:32]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:32]configsip: 0, SPIWP:0xee [17:26:32]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:32]mode:QIO, clock div:1 [17:26:32]load:0x3fff0018,len:4 [17:26:32]load:0x928b2121,len:-1725455839 [17:26:32]1162 mmu set 00010000, pos 00010000 [17:26:32]1162 mmu set 00020000, pos 00020000 [17:26:32]1162 mmu set 00030000, pos 00030000 [17:26:32]1162 mmu set 00040000, pos 00040000 [17:26:32]1162 mmu set 00050000, pos 00050000 [17:26:32]1162 mmu set 00060000, pos 00060000 [17:26:32]1162 mmu set 00070000, pos 00070000 [17:26:32]1162 mmu set 00080000, pos 00080000 [17:26:32]1162 mmu set 00090000, pos 00090000 [17:26:32]1162 mmu set 000a0000, pos 000a0000 [17:26:32]1162 mmu set 000b0000, pos 000b0000 [17:26:32]1162 mmu set 000c0000, pos 000c0000 [17:26:32]1162 mmu set 000d0000, pos 000d0000 [17:26:32]1162 mmu set 000e0000, pos 000e0000 [17:26:32]1162 mmu set 000f0000, pos 000f0000 [17:26:32]1162 mmu set 00100000, pos 00100000 [17:26:32]1162 mmu set 00110000, pos 00110000 [17:26:32]ets Jun 8 2016 00:22:57 [17:26:32] [17:26:32]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:32]configsip: 0, SPIWP:0xee [17:26:32]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:32]mode:QIO, clock div:1 [17:26:32]load:0x3fff0018,len:4 [17:26:32]load:0x928b2121,len:-1725455839 [17:26:32]1162 mmu set 00010000, pos 00010000 [17:26:32]1162 mmu set 00020000, pos 00020000 [17:26:32]1162 mmu set 00030000, pos 00030000 [17:26:32]1162 mmu set 00040000, pos 00040000 [17:26:32]1162 mmu set 00050000, pos 00050000 [17:26:32]1162 mmu set 00060000, pos 00060000 [17:26:32]1162 mmu set 00070000, pos 00070000 [17:26:32]1162 mmu set 00080000, pos 00080000 [17:26:32]1162 mmu set 00090000, pos 00090000 [17:26:32]1162 mmu set 000a0000, pos 000a0000 [17:26:32]1162 mmu set 000b0000, pos 000b0000 [17:26:32]1162 mmu set 000c0000, pos 000c0000 [17:26:32]1162 mmu set 000d0000, pos 000d0000 [17:26:32]1162 mmu set 000e0000, pos 000e0000 [17:26:32]1162 mmu set 000f0000, pos 000f0000 [17:26:33]1162 mmu set 00100000, pos 00100000 [17:26:33]1162 mmu set 00110000, pos 00110000 [17:26:33]ets Jun 8 2016 00:22:57 [17:26:33] [17:26:33]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:33]configsip: 0, SPIWP:0xee [17:26:33]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:33]mode:QIO, clock div:1 [17:26:33]load:0x3fff0018,len:4 [17:26:33]load:0x928b2121,len:-1725455839 [17:26:33]1162 mmu set 00010000, pos 00010000 [17:26:33]1162 mmu set 00020000, pos 00020000 [17:26:33]1162 mmu set 00030000, pos 00030000 [17:26:33]1162 mmu set 00040000, pos 00040000 [17:26:33]1162 mmu set 00050000, pos 00050000 [17:26:33]1162 mmu set 00060000, pos 00060000 [17:26:33]1162 mmu set 00070000, pos 00070000 [17:26:33]1162 mmu set 00080000, pos 00080000 [17:26:33]1162 mmu set 00090000, pos 00090000 [17:26:33]1162 mmu set 000a0000, pos 000a0000 [17:26:33]1162 mmu set 000b0000, pos 000b0000 [17:26:33]1162 mmu set 000c0000, pos 000c0000 [17:26:33]1162 mmu set 000d0000, pos 000d0000 [17:26:33]1162 mmu set 000e0000, pos 000e0000 [17:26:33]1162 mmu set 000f0000, pos 000f0000 [17:26:33]1162 mmu set 00100000, pos 00100000 [17:26:33]1162 mmu set 00110000, pos 00110000 [17:26:33]ets Jun 8 2016 00:22:57 [17:26:33] [17:26:33]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:33]configsip: 0, SPIWP:0xee [17:26:33]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:33]mode:QIO, clock div:1 [17:26:33]load:0x3fff0018,len:4 [17:26:33]load:0x928b2121,len:-1725455839 [17:26:33]1162 mmu set 00010000, pos 00010000 [17:26:33]1162 mmu set 00020000, pos 00020000 [17:26:33]1162 mmu set 00030000, pos 00030000 [17:26:33]1162 mmu set 00040000, pos 00040000 [17:26:33]1162 mmu set 00050000, pos 00050000 [17:26:33]1162 mmu set 00060000, pos 00060000 [17:26:33]1162 mmu set 00070000, pos 00070000 [17:26:33]1162 mmu set 00080000, pos 00080000 [17:26:33]1162 mmu set 00090000, pos 00090000 [17:26:33]1162 mmu set 000a0000, pos 000a0000 [17:26:33]1162 mmu set 000b0000, pos 000b0000 [17:26:33]1162 mmu set 000c0000, pos 000c0000 [17:26:33]1162 mmu set 000d0000, pos 000d0000 [17:26:33]1162 mmu set 000e0000, pos 000e0000 [17:26:33]1162 mmu set 000f0000, pos 000f0000 [17:26:33]1162 mmu set 00100000, pos 00100000 [17:26:33]1162 mmu set 00110000, pos 00110000 [17:26:33]ets Jun 8 2016 00:22:57 [17:26:33] [17:26:33]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:33]configsip: 0, SPIWP:0xee [17:26:33]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:33]mode:QIO, clock div:1 [17:26:33]load:0x3fff0018,len:4 [17:26:33]load:0x928b2121,len:-1725455839 [17:26:33]1162 mmu set 00010000, pos 00010000 [17:26:33]1162 mmu set 00020000, pos 00020000 [17:26:33]1162 mmu set 00030000, pos 00030000 [17:26:33]1162 mmu set 00040000, pos 00040000 [17:26:33]1162 mmu set 00050000, pos 00050000 [17:26:33]1162 mmu set 00060000, pos 00060000 [17:26:33]1162 mmu set 00070000, pos 00070000 [17:26:33]1162 mmu set 00080000, pos 00080000 [17:26:33]1162 mmu set 00090000, pos 00090000 [17:26:33]1162 mmu set 000a0000, pos 000a0000 [17:26:34]1162 mmu set 000b0000, pos 000b0000 [17:26:34]1162 mmu set 000c0000, pos 000c0000 [17:26:34]1162 mmu set 000d0000, pos 000d0000 [17:26:34]1162 mmu set 000e0000, pos 000e0000 [17:26:34]1162 mmu set 000f0000, pos 000f0000 [17:26:34]1162 mmu set 00100000, pos 00100000 [17:26:34]1162 mmu set 00110000, pos 00110000 [17:26:34]ets Jun 8 2016 00:22:57 [17:26:34] [17:26:34]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:34]configsip: 0, SPIWP:0xee [17:26:34]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:34]mode:QIO, clock div:1 [17:26:34]load:0x3fff0018,len:4 [17:26:34]load:0x928b2121,len:-1725455839 [17:26:34]1162 mmu set 00010000, pos 00010000 [17:26:34]1162 mmu set 00020000, pos 00020000 [17:26:34]1162 mmu set 00030000, pos 00030000 [17:26:34]1162 mmu set 00040000, pos 00040000 [17:26:34]1162 mmu set 00050000, pos 00050000 [17:26:34]1162 mmu set 00060000, pos 00060000 [17:26:34]1162 mmu set 00070000, pos 00070000 [17:26:34]1162 mmu set 00080000, pos 00080000 [17:26:34]1162 mmu set 00090000, pos 00090000 [17:26:34]1162 mmu set 000a0000, pos 000a0000 [17:26:34]1162 mmu set 000b0000, pos 000b0000 [17:26:34]1162 mmu set 000c0000, pos 000c0000 [17:26:34]1162 mmu set 000d0000, pos 000d0000 [17:26:34]1162 mmu set 000e0000, pos 000e0000 [17:26:34]1162 mmu set 000f0000, pos 000f0000 [17:26:34]1162 mmu set 00100000, pos 00100000 [17:26:34]1162 mmu set 00110000, pos 00110000 [17:26:34]ets Jun 8 2016 00:22:57 [17:26:34] [17:26:34]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:34]configsip: 0, SPIWP:0xee [17:26:34]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:34]mode:QIO, clock div:1 [17:26:34]load:0x3fff0018,len:4 [17:26:34]load:0x928b2121,len:-1725455839 [17:26:34]1162 mmu set 00010000, pos 00010000 [17:26:34]1162 mmu set 00020000, pos 00020000 [17:26:34]1162 mmu set 00030000, pos 00030000 [17:26:34]1162 mmu set 00040000, pos 00040000 [17:26:34]1162 mmu set 00050000, pos 00050000 [17:26:34]1162 mmu set 00060000, pos 00060000 [17:26:34]1162 mmu set 00070000, pos 00070000 [17:26:34]1162 mmu set 00080000, pos 00080000 [17:26:34]1162 mmu set 00090000, pos 00090000 [17:26:34]1162 mmu set 000a0000, pos 000a0000 [17:26:34]1162 mmu set 000b0000, pos 000b0000 [17:26:34]1162 mmu set 000c0000, pos 000c0000 [17:26:34]1162 mmu set 000d0000, pos 000d0000 [17:26:34]1162 mmu set 000e0000, pos 000e0000 [17:26:34]1162 mmu set 000f0000, pos 000f0000 [17:26:34]1162 mmu set 00100000, pos 00100000 [17:26:34]1162 mmu set 00110000, pos 00110000 [17:26:34]ets Jun 8 2016 00:22:57 [17:26:34] [17:26:34]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:34]configsip: 0, SPIWP:0xee [17:26:34]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:34]mode:QIO, clock div:1 [17:26:34]load:0x3fff0018,len:4 [17:26:34]load:0x928b2121,len:-1725455839 [17:26:34]1162 mmu set 00010000, pos 00010000 [17:26:34]1162 mmu set 00020000, pos 00020000 [17:26:34]1162 mmu set 00030000, pos 00030000 [17:26:34]1162 mmu set 00040000, pos 00040000 [17:26:34]1162 mmu set 00050000, pos 00050000 [17:26:35]1162 mmu set 00060000, pos 00060000 [17:26:35]1162 mmu set 00070000, pos 00070000 [17:26:35]1162 mmu set 00080000, pos 00080000 [17:26:35]1162 mmu set 00090000, pos 00090000 [17:26:35]1162 mmu set 000a0000, pos 000a0000 [17:26:35]1162 mmu set 000b0000, pos 000b0000 [17:26:35]1162 mmu set 000c0000, pos 000c0000 [17:26:35]1162 mmu set 000d0000, pos 000d0000 [17:26:35]1162 mmu set 000e0000, pos 000e0000 [17:26:35]1162 mmu set 000f0000, pos 000f0000 [17:26:35]1162 mmu set 00100000, pos 00100000 [17:26:35]1162 mmu set 00110000, pos 00110000 [17:26:35]ets Jun 8 2016 00:22:57 [17:26:35] [17:26:35]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:35]configsip: 0, SPIWP:0xee [17:26:35]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:35]mode:QIO, clock div:1 [17:26:35]load:0x3fff0018,len:4 [17:26:35]load:0x928b2121,len:-1725455839 [17:26:35]1162 mmu set 00010000, pos 00010000 [17:26:35]1162 mmu set 00020000, pos 00020000 [17:26:35]1162 mmu set 00030000, pos 00030000 [17:26:35]1162 mmu set 00040000, pos 00040000 [17:26:35]1162 mmu set 00050000, pos 00050000 [17:26:35]1162 mmu set 00060000, pos 00060000 [17:26:35]1162 mmu set 00070000, pos 00070000 [17:26:35]1162 mmu set 00080000, pos 00080000 [17:26:35]1162 mmu set 00090000, pos 00090000 [17:26:35]1162 mmu set 000a0000, pos 000a0000 [17:26:35]1162 mmu set 000b0000, pos 000b0000 [17:26:35]1162 mmu set 000c0000, pos 000c0000 [17:26:35]1162 mmu set 000d0000, pos 000d0000 [17:26:35]1162 mmu set 000e0000, pos 000e0000 [17:26:35]1162 mmu set 000f0000, pos 000f0000 [17:26:35]1162 mmu set 00100000, pos 00100000 [17:26:35]1162 mmu set 00110000, pos 00110000 [17:26:35]ets Jun 8 2016 00:22:57 [17:26:35] [17:26:35]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:35]configsip: 0, SPIWP:0xee [17:26:35]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:35]mode:QIO, clock div:1 [17:26:35]load:0x3fff0018,len:4 [17:26:35]load:0x928b2121,len:-1725455839 [17:26:35]1162 mmu set 00010000, pos 00010000 [17:26:35]1162 mmu set 00020000, pos 00020000 [17:26:35]1162 mmu set 00030000, pos 00030000 [17:26:35]1162 mmu set 00040000, pos 00040000 [17:26:35]1162 mmu set 00050000, pos 00050000 [17:26:35]1162 mmu set 00060000, pos 00060000 [17:26:35]1162 mmu set 00070000, pos 00070000 [17:26:35]1162 mmu set 00080000, pos 00080000 [17:26:35]1162 mmu set 00090000, pos 00090000 [17:26:35]1162 mmu set 000a0000, pos 000a0000 [17:26:35]1162 mmu set 000b0000, pos 000b0000 [17:26:35]1162 mmu set 000c0000, pos 000c0000 [17:26:35]1162 mmu set 000d0000, pos 000d0000 [17:26:35]1162 mmu set 000e0000, pos 000e0000 [17:26:35]1162 mmu set 000f0000, pos 000f0000 [17:26:35]1162 mmu set 00100000, pos 00100000 [17:26:35]1162 mmu set 00110000, pos 00110000 [17:26:35]ets Jun 8 2016 00:22:57 [17:26:35] [17:26:35]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:36]configsip: 0, SPIWP:0xee [17:26:36]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:36]mode:QIO, clock div:1 [17:26:36]load:0x3fff0018,len:4 [17:26:36]load:0x928b2121,len:-1725455839 [17:26:36]1162 mmu set 00010000, pos 00010000 [17:26:36]1162 mmu set 00020000, pos 00020000 [17:26:36]1162 mmu set 00030000, pos 00030000 [17:26:36]1162 mmu set 00040000, pos 00040000 [17:26:36]1162 mmu set 00050000, pos 00050000 [17:26:36]1162 mmu set 00060000, pos 00060000 [17:26:36]1162 mmu set 00070000, pos 00070000 [17:26:36]1162 mmu set 00080000, pos 00080000 [17:26:36]1162 mmu set 00090000, pos 00090000 [17:26:36]1162 mmu set 000a0000, pos 000a0000 [17:26:36]1162 mmu set 000b0000, pos 000b0000 [17:26:36]1162 mmu set 000c0000, pos 000c0000 [17:26:36]1162 mmu set 000d0000, pos 000d0000 [17:26:36]1162 mmu set 000e0000, pos 000e0000 [17:26:36]1162 mmu set 000f0000, pos 000f0000 [17:26:36]1162 mmu set 00100000, pos 00100000 [17:26:36]1162 mmu set 00110000, pos 00110000 [17:26:36]ets Jun 8 2016 00:22:57 [17:26:36] [17:26:36]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:36]configsip: 0, SPIWP:0xee [17:26:36]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:36]mode:QIO, clock div:1 [17:26:36]load:0x3fff0018,len:4 [17:26:36]load:0x928b2121,len:-1725455839 [17:26:36]1162 mmu set 00010000, pos 00010000 [17:26:36]1162 mmu set 00020000, pos 00020000 [17:26:36]1162 mmu set 00030000, pos 00030000 [17:26:36]1162 mmu set 00040000, pos 00040000 [17:26:36]1162 mmu set 00050000, pos 00050000 [17:26:36]1162 mmu set 00060000, pos 00060000 [17:26:36]1162 mmu set 00070000, pos 00070000 [17:26:36]1162 mmu set 00080000, pos 00080000 [17:26:36]1162 mmu set 00090000, pos 00090000 [17:26:36]1162 mmu set 000a0000, pos 000a0000 [17:26:36]1162 mmu set 000b0000, pos 000b0000 [17:26:36]1162 mmu set 000c0000, pos 000c0000 [17:26:36]1162 mmu set 000d0000, pos 000d0000 [17:26:36]1162 mmu set 000e0000, pos 000e0000 [17:26:36]1162 mmu set 000f0000, pos 000f0000 [17:26:36]1162 mmu set 00100000, pos 00100000 [17:26:36]1162 mmu set 00110000, pos 00110000 [17:26:36]ets Jun 8 2016 00:22:57 [17:26:36] [17:26:36]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:36]configsip: 0, SPIWP:0xee [17:26:36]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:36]mode:QIO, clock div:1 [17:26:36]load:0x3fff0018,len:4 [17:26:36]load:0x928b2121,len:-1725455839 [17:26:36]1162 mmu set 00010000, pos 00010000 [17:26:36]1162 mmu set 00020000, pos 00020000 [17:26:36]1162 mmu set 00030000, pos 00030000 [17:26:36]1162 mmu set 00040000, pos 00040000 [17:26:36]1162 mmu set 00050000, pos 00050000 [17:26:36]1162 mmu set 00060000, pos 00060000 [17:26:36]1162 mmu set 00070000, pos 00070000 [17:26:36]1162 mmu set 00080000, pos 00080000 [17:26:36]1162 mmu set 00090000, pos 00090000 [17:26:36]1162 mmu set 000a0000, pos 000a0000 [17:26:36]1162 mmu set 000b0000, pos 000b0000 [17:26:36]1162 mmu set 000c0000, pos 000c0000 [17:26:37]1162 mmu set 000d0000, pos 000d0000 [17:26:37]1162 mmu set 000e0000, pos 000e0000 [17:26:37]1162 mmu set 000f0000, pos 000f0000 [17:26:37]1162 mmu set 00100000, pos 00100000 [17:26:37]1162 mmu set 00110000, pos 00110000 [17:26:37]ets Jun 8 2016 00:22:57 [17:26:37] [17:26:37]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:37]configsip: 0, SPIWP:0xee [17:26:37]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:37]mode:QIO, clock div:1 [17:26:37]load:0x3fff0018,len:4 [17:26:37]load:0x928b2121,len:-1725455839 [17:26:37]1162 mmu set 00010000, pos 00010000 [17:26:37]1162 mmu set 00020000, pos 00020000 [17:26:37]1162 mmu set 00030000, pos 00030000 [17:26:37]1162 mmu set 00040000, pos 00040000 [17:26:37]1162 mmu set 00050000, pos 00050000 [17:26:37]1162 mmu set 00060000, pos 00060000 [17:26:37]1162 mmu set 00070000, pos 00070000 [17:26:37]1162 mmu set 00080000, pos 00080000 [17:26:37]1162 mmu set 00090000, pos 00090000 [17:26:37]1162 mmu set 000a0000, pos 000a0000 [17:26:37]1162 mmu set 000b0000, pos 000b0000 [17:26:37]1162 mmu set 000c0000, pos 000c0000 [17:26:37]1162 mmu set 000d0000, pos 000d0000 [17:26:37]1162 mmu set 000e0000, pos 000e0000 [17:26:37]1162 mmu set 000f0000, pos 000f0000 [17:26:37]1162 mmu set 00100000, pos 00100000 [17:26:37]1162 mmu set 00110000, pos 00110000 [17:26:37]ets Jun 8 2016 00:22:57 [17:26:37] [17:26:37]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:37]configsip: 0, SPIWP:0xee [17:26:37]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:37]mode:QIO, clock div:1 [17:26:37]load:0x3fff0018,len:4 [17:26:37]load:0x928b2121,len:-1725455839 [17:26:37]1162 mmu set 00010000, pos 00010000 [17:26:37]1162 mmu set 00020000, pos 00020000 [17:26:37]1162 mmu set 00030000, pos 00030000 [17:26:37]1162 mmu set 00040000, pos 00040000 [17:26:37]1162 mmu set 00050000, pos 00050000 [17:26:37]1162 mmu set 00060000, pos 00060000 [17:26:37]1162 mmu set 00070000, pos 00070000 [17:26:37]1162 mmu set 00080000, pos 00080000 [17:26:37]1162 mmu set 00090000, pos 00090000 [17:26:37]1162 mmu set 000a0000, pos 000a0000 [17:26:37]1162 mmu set 000b0000, pos 000b0000 [17:26:37]1162 mmu set 000c0000, pos 000c0000 [17:26:37]1162 mmu set 000d0000, pos 000d0000 [17:26:37]1162 mmu set 000e0000, pos 000e0000 [17:26:37]1162 mmu set 000f0000, pos 000f0000 [17:26:37]1162 mmu set 00100000, pos 00100000 [17:26:37]1162 mmu set 00110000, pos 00110000 [17:26:37]ets Jun 8 2016 00:22:57 [17:26:37] [17:26:37]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:37]configsip: 0, SPIWP:0xee [17:26:37]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:37]mode:QIO, clock div:1 [17:26:37]load:0x3fff0018,len:4 [17:26:37]load:0x928b2121,len:-1725455839 [17:26:37]1162 mmu set 00010000, pos 00010000 [17:26:37]1162 mmu set 00020000, pos 00020000 [17:26:37]1162 mmu set 00030000, pos 00030000 [17:26:37]1162 mmu set 00040000, pos 00040000 [17:26:37]1162 mmu set 00050000, pos 00050000 [17:26:37]1162 mmu set 00060000, pos 00060000 [17:26:37]1162 mmu set 00070000, pos 00070000 [17:26:38]1162 mmu set 00080000, pos 00080000 [17:26:38]1162 mmu set 00090000, pos 00090000 [17:26:38]1162 mmu set 000a0000, pos 000a0000 [17:26:38]1162 mmu set 000b0000, pos 000b0000 [17:26:38]1162 mmu set 000c0000, pos 000c0000 [17:26:38]1162 mmu set 000d0000, pos 000d0000 [17:26:38]1162 mmu set 000e0000, pos 000e0000 [17:26:38]1162 mmu set 000f0000, pos 000f0000 [17:26:38]1162 mmu set 00100000, pos 00100000 [17:26:38]1162 mmu set 00110000, pos 00110000 [17:26:38]ets Jun 8 2016 00:22:57 [17:26:38] [17:26:38]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:38]configsip: 0, SPIWP:0xee [17:26:38]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:38]mode:QIO, clock div:1 [17:26:38]load:0x3fff0018,len:4 [17:26:38]load:0x928b2121,len:-1725455839 [17:26:38]1162 mmu set 00010000, pos 00010000 [17:26:38]1162 mmu set 00020000, pos 00020000 [17:26:38]1162 mmu set 00030000, pos 00030000 [17:26:38]1162 mmu set 00040000, pos 00040000 [17:26:38]1162 mmu set 00050000, pos 00050000 [17:26:38]1162 mmu set 00060000, pos 00060000 [17:26:38]1162 mmu set 00070000, pos 00070000 [17:26:38]1162 mmu set 00080000, pos 00080000 [17:26:38]1162 mmu set 00090000, pos 00090000 [17:26:38]1162 mmu set 000a0000, pos 000a0000 [17:26:38]1162 mmu set 000b0000, pos 000b0000 [17:26:38]1162 mmu set 000c0000, pos 000c0000 [17:26:38]1162 mmu set 000d0000, pos 000d0000 [17:26:38]1162 mmu set 000e0000, pos 000e0000 [17:26:38]1162 mmu set 000f0000, pos 000f0000 [17:26:38]1162 mmu set 00100000, pos 00100000 [17:26:38]1162 mmu set 00110000, pos 00110000 [17:26:38]ets Jun 8 2016 00:22:57 [17:26:38] [17:26:38]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:38]configsip: 0, SPIWP:0xee [17:26:38]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:38]mode:QIO, clock div:1 [17:26:38]load:0x3fff0018,len:4 [17:26:38]load:0x928b2121,len:-1725455839 [17:26:38]1162 mmu set 00010000, pos 00010000 [17:26:38]1162 mmu set 00020000, pos 00020000 [17:26:38]1162 mmu set 00030000, pos 00030000 [17:26:38]1162 mmu set 00040000, pos 00040000 [17:26:38]1162 mmu set 00050000, pos 00050000 [17:26:38]1162 mmu set 00060000, pos 00060000 [17:26:38]1162 mmu set 00070000, pos 00070000 [17:26:38]1162 mmu set 00080000, pos 00080000 [17:26:38]1162 mmu set 00090000, pos 00090000 [17:26:38]1162 mmu set 000a0000, pos 000a0000 [17:26:38]1162 mmu set 000b0000, pos 000b0000 [17:26:38]1162 mmu set 000c0000, pos 000c0000 [17:26:38]1162 mmu set 000d0000, pos 000d0000 [17:26:38]1162 mmu set 000e0000, pos 000e0000 [17:26:38]1162 mmu set 000f0000, pos 000f0000 [17:26:38]1162 mmu set 00100000, pos 00100000 [17:26:38]1162 mmu set 00110000, pos 00110000 [17:26:38]ets Jun 8 2016 00:22:57 [17:26:38] [17:26:38]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:38]configsip: 0, SPIWP:0xee [17:26:38]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:38]mode:QIO, clock div:1 [17:26:38]load:0x3fff0018,len:4 [17:26:38]load:0x928b2121,len:-1725455839 [17:26:38]1162 mmu set 00010000, pos 00010000 [17:26:38]1162 mmu set 00020000, pos 00020000 [17:26:39]1162 mmu set 00030000, pos 00030000 [17:26:39]1162 mmu set 00040000, pos 00040000 [17:26:39]1162 mmu set 00050000, pos 00050000 [17:26:39]1162 mmu set 00060000, pos 00060000 [17:26:39]1162 mmu set 00070000, pos 00070000 [17:26:39]1162 mmu set 00080000, pos 00080000 [17:26:39]1162 mmu set 00090000, pos 00090000 [17:26:39]1162 mmu set 000a0000, pos 000a0000 [17:26:39]1162 mmu set 000b0000, pos 000b0000 [17:26:39]1162 mmu set 000c0000, pos 000c0000 [17:26:39]1162 mmu set 000d0000, pos 000d0000 [17:26:39]1162 mmu set 000e0000, pos 000e0000 [17:26:39]1162 mmu set 000f0000, pos 000f0000 [17:26:39]1162 mmu set 00100000, pos 00100000 [17:26:39]1162 mmu set 00110000, pos 00110000 [17:26:39]ets Jun 8 2016 00:22:57 [17:26:39] [17:26:39]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:39]configsip: 0, SPIWP:0xee [17:26:39]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:39]mode:QIO, clock div:1 [17:26:39]load:0x3fff0018,len:4 [17:26:39]load:0x928b2121,len:-1725455839 [17:26:39]1162 mmu set 00010000, pos 00010000 [17:26:39]1162 mmu set 00020000, pos 00020000 [17:26:39]1162 mmu set 00030000, pos 00030000 [17:26:39]1162 mmu set 00040000, pos 00040000 [17:26:39]1162 mmu set 00050000, pos 00050000 [17:26:39]1162 mmu set 00060000, pos 00060000 [17:26:39]1162 mmu set 00070000, pos 00070000 [17:26:39]1162 mmu set 00080000, pos 00080000 [17:26:39]1162 mmu set 00090000, pos 00090000 [17:26:39]1162 mmu set 000a0000, pos 000a0000 [17:26:39]1162 mmu set 000b0000, pos 000b0000 [17:26:39]1162 mmu set 000c0000, pos 000c0000 [17:26:39]1162 mmu set 000d0000, pos 000d0000 [17:26:39]1162 mmu set 000e0000, pos 000e0000 [17:26:39]1162 mmu set 000f0000, pos 000f0000 [17:26:39]1162 mmu set 00100000, pos 00100000 [17:26:39]1162 mmu set 00110000, pos 00110000 [17:26:39]ets Jun 8 2016 00:22:57 [17:26:39] [17:26:39]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:39]configsip: 0, SPIWP:0xee [17:26:39]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:39]mode:QIO, clock div:1 [17:26:39]load:0x3fff0018,len:4 [17:26:39]load:0x928b2121,len:-1725455839 [17:26:39]1162 mmu set 00010000, pos 00010000 [17:26:39]1162 mmu set 00020000, pos 00020000 [17:26:39]1162 mmu set 00030000, pos 00030000 [17:26:39]1162 mmu set 00040000, pos 00040000 [17:26:39]1162 mmu set 00050000, pos 00050000 [17:26:39]1162 mmu set 00060000, pos 00060000 [17:26:39]1162 mmu set 00070000, pos 00070000 [17:26:39]1162 mmu set 00080000, pos 00080000 [17:26:39]1162 mmu set 00090000, pos 00090000 [17:26:39]1162 mmu set 000a0000, pos 000a0000 [17:26:39]1162 mmu set 000b0000, pos 000b0000 [17:26:39]1162 mmu set 000c0000, pos 000c0000 [17:26:39]1162 mmu set 000d0000, pos 000d0000 [17:26:39]1162 mmu set 000e0000, pos 000e0000 [17:26:39]1162 mmu set 000f0000, pos 000f0000 [17:26:40]1162 mmu set 00100000, pos 00100000 [17:26:40]1162 mmu set 00110000, pos 00110000 [17:26:40]ets Jun 8 2016 00:22:57 [17:26:40] [17:26:40]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:40]configsip: 0, SPIWP:0xee [17:26:40]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:40]mode:QIO, clock div:1 [17:26:40]load:0x3fff0018,len:4 [17:26:40]load:0x928b2121,len:-1725455839 [17:26:40]1162 mmu set 00010000, pos 00010000 [17:26:40]1162 mmu set 00020000, pos 00020000 [17:26:40]1162 mmu set 00030000, pos 00030000 [17:26:40]1162 mmu set 00040000, pos 00040000 [17:26:40]1162 mmu set 00050000, pos 00050000 [17:26:40]1162 mmu set 00060000, pos 00060000 [17:26:40]1162 mmu set 00070000, pos 00070000 [17:26:40]1162 mmu set 00080000, pos 00080000 [17:26:40]1162 mmu set 00090000, pos 00090000 [17:26:40]1162 mmu set 000a0000, pos 000a0000 [17:26:40]1162 mmu set 000b0000, pos 000b0000 [17:26:40]1162 mmu set 000c0000, pos 000c0000 [17:26:40]1162 mmu set 000d0000, pos 000d0000 [17:26:40]1162 mmu set 000e0000, pos 000e0000 [17:26:40]1162 mmu set 000f0000, pos 000f0000 [17:26:40]1162 mmu set 00100000, pos 00100000 [17:26:40]1162 mmu set 00110000, pos 00110000 [17:26:40]ets Jun 8 2016 00:22:57 [17:26:40] [17:26:40]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:40]configsip: 0, SPIWP:0xee [17:26:40]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:40]mode:QIO, clock div:1 [17:26:40]load:0x3fff0018,len:4 [17:26:40]load:0x928b2121,len:-1725455839 [17:26:40]1162 mmu set 00010000, pos 00010000 [17:26:40]1162 mmu set 00020000, pos 00020000 [17:26:40]1162 mmu set 00030000, pos 00030000 [17:26:40]1162 mmu set 00040000, pos 00040000 [17:26:40]1162 mmu set 00050000, pos 00050000 [17:26:40]1162 mmu set 00060000, pos 00060000 [17:26:40]1162 mmu set 00070000, pos 00070000 [17:26:40]1162 mmu set 00080000, pos 00080000 [17:26:40]1162 mmu set 00090000, pos 00090000 [17:26:40]1162 mmu set 000a0000, pos 000a0000 [17:26:40]1162 mmu set 000b0000, pos 000b0000 [17:26:40]1162 mmu set 000c0000, pos 000c0000 [17:26:40]1162 mmu set 000d0000, pos 000d0000 [17:26:40]1162 mmu set 000e0000, pos 000e0000 [17:26:40]1162 mmu set 000f0000, pos 000f0000 [17:26:40]1162 mmu set 00100000, pos 00100000 [17:26:40]1162 mmu set 00110000, pos 00110000 [17:26:40]ets Jun 8 2016 00:22:57 [17:26:40] [17:26:40]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:40]configsip: 0, SPIWP:0xee [17:26:40]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:40]mode:QIO, clock div:1 [17:26:40]load:0x3fff0018,len:4 [17:26:40]load:0x928b2121,len:-1725455839 [17:26:40]1162 mmu set 00010000, pos 00010000 [17:26:40]1162 mmu set 00020000, pos 00020000 [17:26:40]1162 mmu set 00030000, pos 00030000 [17:26:40]1162 mmu set 00040000, pos 00040000 [17:26:40]1162 mmu set 00050000, pos 00050000 [17:26:40]1162 mmu set 00060000, pos 00060000 [17:26:40]1162 mmu set 00070000, pos 00070000 [17:26:40]1162 mmu set 00080000, pos 00080000 [17:26:40]1162 mmu set 00090000, pos 00090000 [17:26:41]1162 mmu set 000a0000, pos 000a0000 [17:26:41]1162 mmu set 000b0000, pos 000b0000 [17:26:41]1162 mmu set 000c0000, pos 000c0000 [17:26:41]1162 mmu set 000d0000, pos 000d0000 [17:26:41]1162 mmu set 000e0000, pos 000e0000 [17:26:41]1162 mmu set 000f0000, pos 000f0000 [17:26:41]1162 mmu set 00100000, pos 00100000 [17:26:41]1162 mmu set 00110000, pos 00110000 [17:26:41]ets Jun 8 2016 00:22:57 [17:26:41] [17:26:41]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:41]configsip: 0, SPIWP:0xee [17:26:41]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:41]mode:QIO, clock div:1 [17:26:41]load:0x3fff0018,len:4 [17:26:41]load:0x928b2121,len:-1725455839 [17:26:41]1162 mmu set 00010000, pos 00010000 [17:26:41]1162 mmu set 00020000, pos 00020000 [17:26:41]1162 mmu set 00030000, pos 00030000 [17:26:41]1162 mmu set 00040000, pos 00040000 [17:26:41]1162 mmu set 00050000, pos 00050000 [17:26:41]1162 mmu set 00060000, pos 00060000 [17:26:41]1162 mmu set 00070000, pos 00070000 [17:26:41]1162 mmu set 00080000, pos 00080000 [17:26:41]1162 mmu set 00090000, pos 00090000 [17:26:41]1162 mmu set 000a0000, pos 000a0000 [17:26:41]1162 mmu set 000b0000, pos 000b0000 [17:26:41]1162 mmu set 000c0000, pos 000c0000 [17:26:41]1162 mmu set 000d0000, pos 000d0000 [17:26:41]1162 mmu set 000e0000, pos 000e0000 [17:26:41]1162 mmu set 000f0000, pos 000f0000 [17:26:41]1162 mmu set 00100000, pos 00100000 [17:26:41]1162 mmu set 00110000, pos 00110000 [17:26:41]ets Jun 8 2016 00:22:57 [17:26:41] [17:26:41]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:41]configsip: 0, SPIWP:0xee [17:26:41]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:41]mode:QIO, clock div:1 [17:26:41]load:0x3fff0018,len:4 [17:26:41]load:0x928b2121,len:-1725455839 [17:26:41]1162 mmu set 00010000, pos 00010000 [17:26:41]1162 mmu set 00020000, pos 00020000 [17:26:41]1162 mmu set 00030000, pos 00030000 [17:26:41]1162 mmu set 00040000, pos 00040000 [17:26:41]1162 mmu set 00050000, pos 00050000 [17:26:41]1162 mmu set 00060000, pos 00060000 [17:26:41]1162 mmu set 00070000, pos 00070000 [17:26:41]1162 mmu set 00080000, pos 00080000 [17:26:41]1162 mmu set 00090000, pos 00090000 [17:26:41]1162 mmu set 000a0000, pos 000a0000 [17:26:41]1162 mmu set 000b0000, pos 000b0000 [17:26:41]1162 mmu set 000c0000, pos 000c0000 [17:26:41]1162 mmu set 000d0000, pos 000d0000 [17:26:41]1162 mmu set 000e0000, pos 000e0000 [17:26:41]1162 mmu set 000f0000, pos 000f0000 [17:26:41]1162 mmu set 00100000, pos 00100000 [17:26:41]1162 mmu set 00110000, pos 00110000 [17:26:41]ets Jun 8 2016 00:22:57 [17:26:41] [17:26:41]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:41]configsip: 0, SPIWP:0xee [17:26:41]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:41]mode:QIO, clock div:1 [17:26:41]load:0x3fff0018,len:4 [17:26:41]load:0x928b2121,len:-1725455839 [17:26:41]1162 mmu set 00010000, pos 00010000 [17:26:41]1162 mmu set 00020000, pos 00020000 [17:26:41]1162 mmu set 00030000, pos 00030000 [17:26:41]1162 mmu set 00040000, pos 00040000 [17:26:42]1162 mmu set 00050000, pos 00050000 [17:26:42]1162 mmu set 00060000, pos 00060000 [17:26:42]1162 mmu set 00070000, pos 00070000 [17:26:42]1162 mmu set 00080000, pos 00080000 [17:26:42]1162 mmu set 00090000, pos 00090000 [17:26:42]1162 mmu set 000a0000, pos 000a0000 [17:26:42]1162 mmu set 000b0000, pos 000b0000 [17:26:42]1162 mmu set 000c0000, pos 000c0000 [17:26:42]1162 mmu set 000d0000, pos 000d0000 [17:26:42]1162 mmu set 000e0000, pos 000e0000 [17:26:42]1162 mmu set 000f0000, pos 000f0000 [17:26:42]1162 mmu set 00100000, pos 00100000 [17:26:42]1162 mmu set 00110000, pos 00110000 [17:26:42]ets Jun 8 2016 00:22:57 [17:26:42] [17:26:42]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:42]configsip: 0, SPIWP:0xee [17:26:42]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:42]mode:QIO, clock div:1 [17:26:42]load:0x3fff0018,len:4 [17:26:42]load:0x928b2121,len:-1725455839 [17:26:42]1162 mmu set 00010000, pos 00010000 [17:26:42]1162 mmu set 00020000, pos 00020000 [17:26:42]1162 mmu set 00030000, pos 00030000 [17:26:42]1162 mmu set 00040000, pos 00040000 [17:26:42]1162 mmu set 00050000, pos 00050000 [17:26:42]1162 mmu set 00060000, pos 00060000 [17:26:42]1162 mmu set 00070000, pos 00070000 [17:26:42]1162 mmu set 00080000, pos 00080000 [17:26:42]1162 mmu set 00090000, pos 00090000 [17:26:42]1162 mmu set 000a0000, pos 000a0000 [17:26:42]1162 mmu set 000b0000, pos 000b0000 [17:26:42]1162 mmu set 000c0000, pos 000c0000 [17:26:42]1162 mmu set 000d0000, pos 000d0000 [17:26:42]1162 mmu set 000e0000, pos 000e0000 [17:26:42]1162 mmu set 000f0000, pos 000f0000 [17:26:42]1162 mmu set 00100000, pos 00100000 [17:26:42]1162 mmu set 00110000, pos 00110000 [17:26:42]ets Jun 8 2016 00:22:57 [17:26:42] [17:26:42]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:42]configsip: 0, SPIWP:0xee [17:26:42]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:42]mode:QIO, clock div:1 [17:26:42]load:0x3fff0018,len:4 [17:26:42]load:0x928b2121,len:-1725455839 [17:26:42]1162 mmu set 00010000, pos 00010000 [17:26:42]1162 mmu set 00020000, pos 00020000 [17:26:42]1162 mmu set 00030000, pos 00030000 [17:26:42]1162 mmu set 00040000, pos 00040000 [17:26:42]1162 mmu set 00050000, pos 00050000 [17:26:42]1162 mmu set 00060000, pos 00060000 [17:26:42]1162 mmu set 00070000, pos 00070000 [17:26:42]1162 mmu set 00080000, pos 00080000 [17:26:42]1162 mmu set 00090000, pos 00090000 [17:26:42]1162 mmu set 000a0000, pos 000a0000 [17:26:42]1162 mmu set 000b0000, pos 000b0000 [17:26:42]1162 mmu set 000c0000, pos 000c0000 [17:26:42]1162 mmu set 000d0000, pos 000d0000 [17:26:42]1162 mmu set 000e0000, pos 000e0000 [17:26:42]1162 mmu set 000f0000, pos 000f0000 [17:26:42]1162 mmu set 00100000, pos 00100000 [17:26:42]1162 mmu set 00110000, pos 00110000 [17:26:43]ets Jun 8 2016 00:22:57 [17:26:43] [17:26:43]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:43]configsip: 0, SPIWP:0xee [17:26:43]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:43]mode:QIO, clock div:1 [17:26:43]load:0x3fff0018,len:4 [17:26:43]load:0x928b2121,len:-1725455839 [17:26:43]1162 mmu set 00010000, pos 00010000 [17:26:43]1162 mmu set 00020000, pos 00020000 [17:26:43]1162 mmu set 00030000, pos 00030000 [17:26:43]1162 mmu set 00040000, pos 00040000 [17:26:43]1162 mmu set 00050000, pos 00050000 [17:26:43]1162 mmu set 00060000, pos 00060000 [17:26:43]1162 mmu set 00070000, pos 00070000 [17:26:43]1162 mmu set 00080000, pos 00080000 [17:26:43]1162 mmu set 00090000, pos 00090000 [17:26:43]1162 mmu set 000a0000, pos 000a0000 [17:26:43]1162 mmu set 000b0000, pos 000b0000 [17:26:43]1162 mmu set 000c0000, pos 000c0000 [17:26:43]1162 mmu set 000d0000, pos 000d0000 [17:26:43]1162 mmu set 000e0000, pos 000e0000 [17:26:43]1162 mmu set 000f0000, pos 000f0000 [17:26:43]1162 mmu set 00100000, pos 00100000 [17:26:43]1162 mmu set 00110000, pos 00110000 [17:26:43]ets Jun 8 2016 00:22:57 [17:26:43] [17:26:43]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:43]configsip: 0, SPIWP:0xee [17:26:43]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:43]mode:QIO, clock div:1 [17:26:43]load:0x3fff0018,len:4 [17:26:43]load:0x928b2121,len:-1725455839 [17:26:43]1162 mmu set 00010000, pos 00010000 [17:26:43]1162 mmu set 00020000, pos 00020000 [17:26:43]1162 mmu set 00030000, pos 00030000 [17:26:43]1162 mmu set 00040000, pos 00040000 [17:26:43]1162 mmu set 00050000, pos 00050000 [17:26:43]1162 mmu set 00060000, pos 00060000 [17:26:43]1162 mmu set 00070000, pos 00070000 [17:26:43]1162 mmu set 00080000, pos 00080000 [17:26:43]1162 mmu set 00090000, pos 00090000 [17:26:43]1162 mmu set 000a0000, pos 000a0000 [17:26:43]1162 mmu set 000b0000, pos 000b0000 [17:26:43]1162 mmu set 000c0000, pos 000c0000 [17:26:43]1162 mmu set 000d0000, pos 000d0000 [17:26:43]1162 mmu set 000e0000, pos 000e0000 [17:26:43]1162 mmu set 000f0000, pos 000f0000 [17:26:43]1162 mmu set 00100000, pos 00100000 [17:26:43]1162 mmu set 00110000, pos 00110000 [17:26:43]ets Jun 8 2016 00:22:57 [17:26:43] [17:26:43]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:43]configsip: 0, SPIWP:0xee [17:26:43]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:43]mode:QIO, clock div:1 [17:26:43]load:0x3fff0018,len:4 [17:26:43]load:0x928b2121,len:-1725455839 [17:26:43]1162 mmu set 00010000, pos 00010000 [17:26:43]1162 mmu set 00020000, pos 00020000 [17:26:43]1162 mmu set 00030000, pos 00030000 [17:26:43]1162 mmu set 00040000, pos 00040000 [17:26:43]1162 mmu set 00050000, pos 00050000 [17:26:43]1162 mmu set 00060000, pos 00060000 [17:26:43]1162 mmu set 00070000, pos 00070000 [17:26:43]1162 mmu set 00080000, pos 00080000 [17:26:43]1162 mmu set 00090000, pos 00090000 [17:26:43]1162 mmu set 000a0000, pos 000a0000 [17:26:43]1162 mmu set 000b0000, pos 000b0000 [17:26:43]1162 mmu set 000c0000, pos 000c0000 [17:26:44]1162 mmu set 000d0000, pos 000d0000 [17:26:44]1162 mmu set 000e0000, pos 000e0000 [17:26:44]1162 mmu set 000f0000, pos 000f0000 [17:26:44]1162 mmu set 00100000, pos 00100000 [17:26:44]1162 mmu set 00110000, pos 00110000 [17:26:44]ets Jun 8 2016 00:22:57 [17:26:44] [17:26:44]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:44]configsip: 0, SPIWP:0xee [17:26:44]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:44]mode:QIO, clock div:1 [17:26:44]load:0x3fff0018,len:4 [17:26:44]load:0x928b2121,len:-1725455839 [17:26:44]1162 mmu set 00010000, pos 00010000 [17:26:44]1162 mmu set 00020000, pos 00020000 [17:26:44]1162 mmu set 00030000, pos 00030000 [17:26:44]1162 mmu set 00040000, pos 00040000 [17:26:44]1162 mmu set 00050000, pos 00050000 [17:26:44]1162 mmu set 00060000, pos 00060000 [17:26:44]1162 mmu set 00070000, pos 00070000 [17:26:44]1162 mmu set 00080000, pos 00080000 [17:26:44]1162 mmu set 00090000, pos 00090000 [17:26:44]1162 mmu set 000a0000, pos 000a0000 [17:26:44]1162 mmu set 000b0000, pos 000b0000 [17:26:44]1162 mmu set 000c0000, pos 000c0000 [17:26:44]1162 mmu set 000d0000, pos 000d0000 [17:26:44]1162 mmu set 000e0000, pos 000e0000 [17:26:44]1162 mmu set 000f0000, pos 000f0000 [17:26:44]1162 mmu set 00100000, pos 00100000 [17:26:44]1162 mmu set 00110000, pos 00110000 [17:26:44]ets Jun 8 2016 00:22:57 [17:26:44] [17:26:44]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:44]configsip: 0, SPIWP:0xee [17:26:44]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:44]mode:QIO, clock div:1 [17:26:44]load:0x3fff0018,len:4 [17:26:44]load:0x928b2121,len:-1725455839 [17:26:44]1162 mmu set 00010000, pos 00010000 [17:26:44]1162 mmu set 00020000, pos 00020000 [17:26:44]1162 mmu set 00030000, pos 00030000 [17:26:44]1162 mmu set 00040000, pos 00040000 [17:26:44]1162 mmu set 00050000, pos 00050000 [17:26:44]1162 mmu set 00060000, pos 00060000 [17:26:44]1162 mmu set 00070000, pos 00070000 [17:26:44]1162 mmu set 00080000, pos 00080000 [17:26:44]1162 mmu set 00090000, pos 00090000 [17:26:44]1162 mmu set 000a0000, pos 000a0000 [17:26:44]1162 mmu set 000b0000, pos 000b0000 [17:26:44]1162 mmu set 000c0000, pos 000c0000 [17:26:44]1162 mmu set 000d0000, pos 000d0000 [17:26:44]1162 mmu set 000e0000, pos 000e0000 [17:26:44]1162 mmu set 000f0000, pos 000f0000 [17:26:44]1162 mmu set 00100000, pos 00100000 [17:26:44]1162 mmu set 00110000, pos 00110000 [17:26:44]ets Jun 8 2016 00:22:57 [17:26:44] [17:26:44]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:44]configsip: 0, SPIWP:0xee [17:26:44]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:44]mode:QIO, clock div:1 [17:26:44]load:0x3fff0018,len:4 [17:26:44]load:0x928b2121,len:-1725455839 [17:26:44]1162 mmu set 00010000, pos 00010000 [17:26:44]1162 mmu set 00020000, pos 00020000 [17:26:44]1162 mmu set 00030000, pos 00030000 [17:26:44]1162 mmu set 00040000, pos 00040000 [17:26:44]1162 mmu set 00050000, pos 00050000 [17:26:44]1162 mmu set 00060000, pos 00060000 [17:26:45]1162 mmu set 00070000, pos 00070000 [17:26:45]1162 mmu set 00080000, pos 00080000 [17:26:45]1162 mmu set 00090000, pos 00090000 [17:26:45]1162 mmu set 000a0000, pos 000a0000 [17:26:45]1162 mmu set 000b0000, pos 000b0000 [17:26:45]1162 mmu set 000c0000, pos 000c0000 [17:26:45]1162 mmu set 000d0000, pos 000d0000 [17:26:45]1162 mmu set 000e0000, pos 000e0000 [17:26:45]1162 mmu set 000f0000, pos 000f0000 [17:26:45]1162 mmu set 00100000, pos 00100000 [17:26:45]1162 mmu set 00110000, pos 00110000 [17:26:45]ets Jun 8 2016 00:22:57 [17:26:45] [17:26:45]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:45]configsip: 0, SPIWP:0xee [17:26:45]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:45]mode:QIO, clock div:1 [17:26:45]load:0x3fff0018,len:4 [17:26:45]load:0x928b2121,len:-1725455839 [17:26:45]1162 mmu set 00010000, pos 00010000 [17:26:45]1162 mmu set 00020000, pos 00020000 [17:26:45]1162 mmu set 00030000, pos 00030000 [17:26:45]1162 mmu set 00040000, pos 00040000 [17:26:45]1162 mmu set 00050000, pos 00050000 [17:26:45]1162 mmu set 00060000, pos 00060000 [17:26:45]1162 mmu set 00070000, pos 00070000 [17:26:45]1162 mmu set 00080000, pos 00080000 [17:26:45]1162 mmu set 00090000, pos 00090000 [17:26:45]1162 mmu set 000a0000, pos 000a0000 [17:26:45]1162 mmu set 000b0000, pos 000b0000 [17:26:45]1162 mmu set 000c0000, pos 000c0000 [17:26:45]1162 mmu set 000d0000, pos 000d0000 [17:26:45]1162 mmu set 000e0000, pos 000e0000 [17:26:45]1162 mmu set 000f0000, pos 000f0000 [17:26:45]1162 mmu set 00100000, pos 00100000 [17:26:45]1162 mmu set 00110000, pos 00110000 [17:26:45]ets Jun 8 2016 00:22:57 [17:26:45] [17:26:45]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:45]configsip: 0, SPIWP:0xee [17:26:45]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:45]mode:QIO, clock div:1 [17:26:45]load:0x3fff0018,len:4 [17:26:45]load:0x928b2121,len:-1725455839 [17:26:45]1162 mmu set 00010000, pos 00010000 [17:26:45]1162 mmu set 00020000, pos 00020000 [17:26:45]1162 mmu set 00030000, pos 00030000 [17:26:45]1162 mmu set 00040000, pos 00040000 [17:26:45]1162 mmu set 00050000, pos 00050000 [17:26:45]1162 mmu set 00060000, pos 00060000 [17:26:45]1162 mmu set 00070000, pos 00070000 [17:26:45]1162 mmu set 00080000, pos 00080000 [17:26:45]1162 mmu set 00090000, pos 00090000 [17:26:45]1162 mmu set 000a0000, pos 000a0000 [17:26:45]1162 mmu set 000b0000, pos 000b0000 [17:26:45]1162 mmu set 000c0000, pos 000c0000 [17:26:45]1162 mmu set 000d0000, pos 000d0000 [17:26:45]1162 mmu set 000e0000, pos 000e0000 [17:26:45]1162 mmu set 000f0000, pos 000f0000 [17:26:45]1162 mmu set 00100000, pos 00100000 [17:26:45]1162 mmu set 00110000, pos 00110000 [17:26:45]ets Jun 8 2016 00:22:57 [17:26:45] [17:26:45]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:45]configsip: 0, SPIWP:0xee [17:26:45]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:45]mode:QIO, clock div:1 [17:26:45]load:0x3fff0018,len:4 [17:26:45]load:0x928b2121,len:-1725455839 [17:26:45]1162 mmu set 00010000, pos 00010000 [17:26:46]1162 mmu set 00020000, pos 00020000 [17:26:46]1162 mmu set 00030000, pos 00030000 [17:26:46]1162 mmu set 00040000, pos 00040000 [17:26:46]1162 mmu set 00050000, pos 00050000 [17:26:46]1162 mmu set 00060000, pos 00060000 [17:26:46]1162 mmu set 00070000, pos 00070000 [17:26:46]1162 mmu set 00080000, pos 00080000 [17:26:46]1162 mmu set 00090000, pos 00090000 [17:26:46]1162 mmu set 000a0000, pos 000a0000 [17:26:46]1162 mmu set 000b0000, pos 000b0000 [17:26:46]1162 mmu set 000c0000, pos 000c0000 [17:26:46]1162 mmu set 000d0000, pos 000d0000 [17:26:46]1162 mmu set 000e0000, pos 000e0000 [17:26:46]1162 mmu set 000f0000, pos 000f0000 [17:26:46]1162 mmu set 00100000, pos 00100000 [17:26:46]1162 mmu set 00110000, pos 00110000 [17:26:46]ets Jun 8 2016 00:22:57 [17:26:46] [17:26:46]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:46]configsip: 0, SPIWP:0xee [17:26:46]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:46]mode:QIO, clock div:1 [17:26:46]load:0x3fff0018,len:4 [17:26:46]load:0x928b2121,len:-1725455839 [17:26:46]1162 mmu set 00010000, pos 00010000 [17:26:46]1162 mmu set 00020000, pos 00020000 [17:26:46]1162 mmu set 00030000, pos 00030000 [17:26:46]1162 mmu set 00040000, pos 00040000 [17:26:46]1162 mmu set 00050000, pos 00050000 [17:26:46]1162 mmu set 00060000, pos 00060000 [17:26:46]1162 mmu set 00070000, pos 00070000 [17:26:46]1162 mmu set 00080000, pos 00080000 [17:26:46]1162 mmu set 00090000, pos 00090000 [17:26:46]1162 mmu set 000a0000, pos 000a0000 [17:26:46]1162 mmu set 000b0000, pos 000b0000 [17:26:46]1162 mmu set 000c0000, pos 000c0000 [17:26:46]1162 mmu set 000d0000, pos 000d0000 [17:26:46]1162 mmu set 000e0000, pos 000e0000 [17:26:46]1162 mmu set 000f0000, pos 000f0000 [17:26:46]1162 mmu set 00100000, pos 00100000 [17:26:46]1162 mmu set 00110000, pos 00110000 [17:26:46]ets Jun 8 2016 00:22:57 [17:26:46] [17:26:46]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:46]configsip: 0, SPIWP:0xee [17:26:46]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:46]mode:QIO, clock div:1 [17:26:46]load:0x3fff0018,len:4 [17:26:46]load:0x928b2121,len:-1725455839 [17:26:46]1162 mmu set 00010000, pos 00010000 [17:26:46]1162 mmu set 00020000, pos 00020000 [17:26:46]1162 mmu set 00030000, pos 00030000 [17:26:46]1162 mmu set 00040000, pos 00040000 [17:26:46]1162 mmu set 00050000, pos 00050000 [17:26:46]1162 mmu set 00060000, pos 00060000 [17:26:46]1162 mmu set 00070000, pos 00070000 [17:26:46]1162 mmu set 00080000, pos 00080000 [17:26:46]1162 mmu set 00090000, pos 00090000 [17:26:46]1162 mmu set 000a0000, pos 000a0000 [17:26:46]1162 mmu set 000b0000, pos 000b0000 [17:26:46]1162 mmu set 000c0000, pos 000c0000 [17:26:46]1162 mmu set 000d0000, pos 000d0000 [17:26:46]1162 mmu set 000e0000, pos 000e0000 [17:26:47]1162 mmu set 000f0000, pos 000f0000 [17:26:47]1162 mmu set 00100000, pos 00100000 [17:26:47]1162 mmu set 00110000, pos 00110000 [17:26:47]ets Jun 8 2016 00:22:57 [17:26:47] [17:26:47]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:47]configsip: 0, SPIWP:0xee [17:26:47]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:47]mode:QIO, clock div:1 [17:26:47]load:0x3fff0018,len:4 [17:26:47]load:0x928b2121,len:-1725455839 [17:26:47]1162 mmu set 00010000, pos 00010000 [17:26:47]1162 mmu set 00020000, pos 00020000 [17:26:47]1162 mmu set 00030000, pos 00030000 [17:26:47]1162 mmu set 00040000, pos 00040000 [17:26:47]1162 mmu set 00050000, pos 00050000 [17:26:47]1162 mmu set 00060000, pos 00060000 [17:26:47]1162 mmu set 00070000, pos 00070000 [17:26:47]1162 mmu set 00080000, pos 00080000 [17:26:47]1162 mmu set 00090000, pos 00090000 [17:26:47]1162 mmu set 000a0000, pos 000a0000 [17:26:47]1162 mmu set 000b0000, pos 000b0000 [17:26:47]1162 mmu set 000c0000, pos 000c0000 [17:26:47]1162 mmu set 000d0000, pos 000d0000 [17:26:47]1162 mmu set 000e0000, pos 000e0000 [17:26:47]1162 mmu set 000f0000, pos 000f0000 [17:26:47]1162 mmu set 00100000, pos 00100000 [17:26:47]1162 mmu set 00110000, pos 00110000 [17:26:47]ets Jun 8 2016 00:22:57 [17:26:47] [17:26:47]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:47]configsip: 0, SPIWP:0xee [17:26:47]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:47]mode:QIO, clock div:1 [17:26:47]load:0x3fff0018,len:4 [17:26:47]load:0x928b2121,len:-1725455839 [17:26:47]1162 mmu set 00010000, pos 00010000 [17:26:47]1162 mmu set 00020000, pos 00020000 [17:26:47]1162 mmu set 00030000, pos 00030000 [17:26:47]1162 mmu set 00040000, pos 00040000 [17:26:47]1162 mmu set 00050000, pos 00050000 [17:26:47]1162 mmu set 00060000, pos 00060000 [17:26:47]1162 mmu set 00070000, pos 00070000 [17:26:47]1162 mmu set 00080000, pos 00080000 [17:26:47]1162 mmu set 00090000, pos 00090000 [17:26:47]1162 mmu set 000a0000, pos 000a0000 [17:26:47]1162 mmu set 000b0000, pos 000b0000 [17:26:47]1162 mmu set 000c0000, pos 000c0000 [17:26:47]1162 mmu set 000d0000, pos 000d0000 [17:26:47]1162 mmu set 000e0000, pos 000e0000 [17:26:47]1162 mmu set 000f0000, pos 000f0000 [17:26:47]1162 mmu set 00100000, pos 00100000 [17:26:47]1162 mmu set 00110000, pos 00110000 [17:26:47]ets Jun 8 2016 00:22:57 [17:26:47] [17:26:47]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:47]configsip: 0, SPIWP:0xee [17:26:47]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:47]mode:QIO, clock div:1 [17:26:47]load:0x3fff0018,len:4 [17:26:47]load:0x928b2121,len:-1725455839 [17:26:47]1162 mmu set 00010000, pos 00010000 [17:26:47]1162 mmu set 00020000, pos 00020000 [17:26:47]1162 mmu set 00030000, pos 00030000 [17:26:47]1162 mmu set 00040000, pos 00040000 [17:26:47]1162 mmu set 00050000, pos 00050000 [17:26:47]1162 mmu set 00060000, pos 00060000 [17:26:47]1162 mmu set 00070000, pos 00070000 [17:26:47]1162 mmu set 00080000, pos 00080000 [17:26:47]1162 mmu set 00090000, pos 00090000 [17:26:48]1162 mmu set 000a0000, pos 000a0000 [17:26:48]1162 mmu set 000b0000, pos 000b0000 [17:26:48]1162 mmu set 000c0000, pos 000c0000 [17:26:48]1162 mmu set 000d0000, pos 000d0000 [17:26:48]1162 mmu set 000e0000, pos 000e0000 [17:26:48]1162 mmu set 000f0000, pos 000f0000 [17:26:48]1162 mmu set 00100000, pos 00100000 [17:26:48]1162 mmu set 00110000, pos 00110000 [17:26:48]ets Jun 8 2016 00:22:57 [17:26:48] [17:26:48]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:48]configsip: 0, SPIWP:0xee [17:26:48]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:48]mode:QIO, clock div:1 [17:26:48]load:0x3fff0018,len:4 [17:26:48]load:0x928b2121,len:-1725455839 [17:26:48]1162 mmu set 00010000, pos 00010000 [17:26:48]1162 mmu set 00020000, pos 00020000 [17:26:48]1162 mmu set 00030000, pos 00030000 [17:26:48]1162 mmu set 00040000, pos 00040000 [17:26:48]1162 mmu set 00050000, pos 00050000 [17:26:48]1162 mmu set 00060000, pos 00060000 [17:26:48]1162 mmu set 00070000, pos 00070000 [17:26:48]1162 mmu set 00080000, pos 00080000 [17:26:48]1162 mmu set 00090000, pos 00090000 [17:26:48]1162 mmu set 000a0000, pos 000a0000 [17:26:48]1162 mmu set 000b0000, pos 000b0000 [17:26:48]1162 mmu set 000c0000, pos 000c0000 [17:26:48]1162 mmu set 000d0000, pos 000d0000 [17:26:48]1162 mmu set 000e0000, pos 000e0000 [17:26:48]1162 mmu set 000f0000, pos 000f0000 [17:26:48]1162 mmu set 00100000, pos 00100000 [17:26:48]1162 mmu set 00110000, pos 00110000 [17:26:48]ets Jun 8 2016 00:22:57 [17:26:48] [17:26:48]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:48]configsip: 0, SPIWP:0xee [17:26:48]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:48]mode:QIO, clock div:1 [17:26:48]load:0x3fff0018,len:4 [17:26:48]load:0x928b2121,len:-1725455839 [17:26:48]1162 mmu set 00010000, pos 00010000 [17:26:48]1162 mmu set 00020000, pos 00020000 [17:26:48]1162 mmu set 00030000, pos 00030000 [17:26:48]1162 mmu set 00040000, pos 00040000 [17:26:48]1162 mmu set 00050000, pos 00050000 [17:26:48]1162 mmu set 00060000, pos 00060000 [17:26:48]1162 mmu set 00070000, pos 00070000 [17:26:48]1162 mmu set 00080000, pos 00080000 [17:26:48]1162 mmu set 00090000, pos 00090000 [17:26:48]1162 mmu set 000a0000, pos 000a0000 [17:26:48]1162 mmu set 000b0000, pos 000b0000 [17:26:48]1162 mmu set 000c0000, pos 000c0000 [17:26:48]1162 mmu set 000d0000, pos 000d0000 [17:26:48]1162 mmu set 000e0000, pos 000e0000 [17:26:48]1162 mmu set 000f0000, pos 000f0000 [17:26:48]1162 mmu set 00100000, pos 00100000 [17:26:48]1162 mmu set 00110000, pos 00110000 [17:26:48]ets Jun 8 2016 00:22:57 [17:26:48] [17:26:48]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:48]configsip: 0, SPIWP:0xee [17:26:48]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:48]mode:QIO, clock div:1 [17:26:48]load:0x3fff0018,len:4 [17:26:48]load:0x928b2121,len:-1725455839 [17:26:48]1162 mmu set 00010000, pos 00010000 [17:26:48]1162 mmu set 00020000, pos 00020000 [17:26:48]1162 mmu set 00030000, pos 00030000 [17:26:49]1162 mmu set 00040000, pos 00040000 [17:26:49]1162 mmu set 00050000, pos 00050000 [17:26:49]1162 mmu set 00060000, pos 00060000 [17:26:49]1162 mmu set 00070000, pos 00070000 [17:26:49]1162 mmu set 00080000, pos 00080000 [17:26:49]1162 mmu set 00090000, pos 00090000 [17:26:49]1162 mmu set 000a0000, pos 000a0000 [17:26:49]1162 mmu set 000b0000, pos 000b0000 [17:26:49]1162 mmu set 000c0000, pos 000c0000 [17:26:49]1162 mmu set 000d0000, pos 000d0000 [17:26:49]1162 mmu set 000e0000, pos 000e0000 [17:26:49]1162 mmu set 000f0000, pos 000f0000 [17:26:49]1162 mmu set 00100000, pos 00100000 [17:26:49]1162 mmu set 00110000, pos 00110000 [17:26:49]ets Jun 8 2016 00:22:57 [17:26:49] [17:26:49]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:49]configsip: 0, SPIWP:0xee [17:26:49]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:49]mode:QIO, clock div:1 [17:26:49]load:0x3fff0018,len:4 [17:26:49]load:0x928b2121,len:-1725455839 [17:26:49]1162 mmu set 00010000, pos 00010000 [17:26:49]1162 mmu set 00020000, pos 00020000 [17:26:49]1162 mmu set 00030000, pos 00030000 [17:26:49]1162 mmu set 00040000, pos 00040000 [17:26:49]1162 mmu set 00050000, pos 00050000 [17:26:49]1162 mmu set 00060000, pos 00060000 [17:26:49]1162 mmu set 00070000, pos 00070000 [17:26:49]1162 mmu set 00080000, pos 00080000 [17:26:49]1162 mmu set 00090000, pos 00090000 [17:26:49]1162 mmu set 000a0000, pos 000a0000 [17:26:49]1162 mmu set 000b0000, pos 000b0000 [17:26:49]1162 mmu set 000c0000, pos 000c0000 [17:26:49]1162 mmu set 000d0000, pos 000d0000 [17:26:49]1162 mmu set 000e0000, pos 000e0000 [17:26:49]1162 mmu set 000f0000, pos 000f0000 [17:26:49]1162 mmu set 00100000, pos 00100000 [17:26:49]1162 mmu set 00110000, pos 00110000 [17:26:49]ets Jun 8 2016 00:22:57 [17:26:49] [17:26:49]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:49]configsip: 0, SPIWP:0xee [17:26:49]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:49]mode:QIO, clock div:1 [17:26:49]load:0x3fff0018,len:4 [17:26:49]load:0x928b2121,len:-1725455839 [17:26:49]1162 mmu set 00010000, pos 00010000 [17:26:49]1162 mmu set 00020000, pos 00020000 [17:26:49]1162 mmu set 00030000, pos 00030000 [17:26:49]1162 mmu set 00040000, pos 00040000 [17:26:49]1162 mmu set 00050000, pos 00050000 [17:26:49]1162 mmu set 00060000, pos 00060000 [17:26:49]1162 mmu set 00070000, pos 00070000 [17:26:49]1162 mmu set 00080000, pos 00080000 [17:26:49]1162 mmu set 00090000, pos 00090000 [17:26:49]1162 mmu set 000a0000, pos 000a0000 [17:26:49]1162 mmu set 000b0000, pos 000b0000 [17:26:49]1162 mmu set 000c0000, pos 000c0000 [17:26:49]1162 mmu set 000d0000, pos 000d0000 [17:26:49]1162 mmu set 000e0000, pos 000e0000 [17:26:49]1162 mmu set 000f0000, pos 000f0000 [17:26:49]1162 mmu set 00100000, pos 00100000 [17:26:50]1162 mmu set 00110000, pos 00110000 [17:26:50]ets Jun 8 2016 00:22:57 [17:26:50] [17:26:50]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:50]configsip: 0, SPIWP:0xee [17:26:50]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:50]mode:QIO, clock div:1 [17:26:50]load:0x3fff0018,len:4 [17:26:50]load:0x928b2121,len:-1725455839 [17:26:50]1162 mmu set 00010000, pos 00010000 [17:26:50]1162 mmu set 00020000, pos 00020000 [17:26:50]1162 mmu set 00030000, pos 00030000 [17:26:50]1162 mmu set 00040000, pos 00040000 [17:26:50]1162 mmu set 00050000, pos 00050000 [17:26:50]1162 mmu set 00060000, pos 00060000 [17:26:50]1162 mmu set 00070000, pos 00070000 [17:26:50]1162 mmu set 00080000, pos 00080000 [17:26:50]1162 mmu set 00090000, pos 00090000 [17:26:50]1162 mmu set 000a0000, pos 000a0000 [17:26:50]1162 mmu set 000b0000, pos 000b0000 [17:26:50]1162 mmu set 000c0000, pos 000c0000 [17:26:50]1162 mmu set 000d0000, pos 000d0000 [17:26:50]1162 mmu set 000e0000, pos 000e0000 [17:26:50]1162 mmu set 000f0000, pos 000f0000 [17:26:50]1162 mmu set 00100000, pos 00100000 [17:26:50]1162 mmu set 00110000, pos 00110000 [17:26:50]ets Jun 8 2016 00:22:57 [17:26:50] [17:26:50]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:50]configsip: 0, SPIWP:0xee [17:26:50]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:50]mode:QIO, clock div:1 [17:26:50]load:0x3fff0018,len:4 [17:26:50]load:0x928b2121,len:-1725455839 [17:26:50]1162 mmu set 00010000, pos 00010000 [17:26:50]1162 mmu set 00020000, pos 00020000 [17:26:50]1162 mmu set 00030000, pos 00030000 [17:26:50]1162 mmu set 00040000, pos 00040000 [17:26:50]1162 mmu set 00050000, pos 00050000 [17:26:50]1162 mmu set 00060000, pos 00060000 [17:26:50]1162 mmu set 00070000, pos 00070000 [17:26:50]1162 mmu set 00080000, pos 00080000 [17:26:50]1162 mmu set 00090000, pos 00090000 [17:26:50]1162 mmu set 000a0000, pos 000a0000 [17:26:50]1162 mmu set 000b0000, pos 000b0000 [17:26:50]1162 mmu set 000c0000, pos 000c0000 [17:26:50]1162 mmu set 000d0000, pos 000d0000 [17:26:50]1162 mmu set 000e0000, pos 000e0000 [17:26:50]1162 mmu set 000f0000, pos 000f0000 [17:26:50]1162 mmu set 00100000, pos 00100000 [17:26:50]1162 mmu set 00110000, pos 00110000 [17:26:50]ets Jun 8 2016 00:22:57 [17:26:50] [17:26:50]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:50]configsip: 0, SPIWP:0xee [17:26:50]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:50]mode:QIO, clock div:1 [17:26:50]load:0x3fff0018,len:4 [17:26:50]load:0x928b2121,len:-1725455839 [17:26:50]1162 mmu set 00010000, pos 00010000 [17:26:50]1162 mmu set 00020000, pos 00020000 [17:26:50]1162 mmu set 00030000, pos 00030000 [17:26:50]1162 mmu set 00040000, pos 00040000 [17:26:50]1162 mmu set 00050000, pos 00050000 [17:26:50]1162 mmu set 00060000, pos 00060000 [17:26:50]1162 mmu set 00070000, pos 00070000 [17:26:50]1162 mmu set 00080000, pos 00080000 [17:26:50]1162 mmu set 00090000, pos 00090000 [17:26:50]1162 mmu set 000a0000, pos 000a0000 [17:26:50]1162 mmu set 000b0000, pos 000b0000 [17:26:51]1162 mmu set 000c0000, pos 000c0000 [17:26:51]1162 mmu set 000d0000, pos 000d0000 [17:26:51]1162 mmu set 000e0000, pos 000e0000 [17:26:51]1162 mmu set 000f0000, pos 000f0000 [17:26:51]1162 mmu set 00100000, pos 00100000 [17:26:51]1162 mmu set 00110000, pos 00110000 [17:26:51]ets Jun 8 2016 00:22:57 [17:26:51] [17:26:51]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:51]configsip: 0, SPIWP:0xee [17:26:51]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:51]mode:QIO, clock div:1 [17:26:51]load:0x3fff0018,len:4 [17:26:51]load:0x928b2121,len:-1725455839 [17:26:51]1162 mmu set 00010000, pos 00010000 [17:26:51]1162 mmu set 00020000, pos 00020000 [17:26:51]1162 mmu set 00030000, pos 00030000 [17:26:51]1162 mmu set 00040000, pos 00040000 [17:26:51]1162 mmu set 00050000, pos 00050000 [17:26:51]1162 mmu set 00060000, pos 00060000 [17:26:51]1162 mmu set 00070000, pos 00070000 [17:26:51]1162 mmu set 00080000, pos 00080000 [17:26:51]1162 mmu set 00090000, pos 00090000 [17:26:51]1162 mmu set 000a0000, pos 000a0000 [17:26:51]1162 mmu set 000b0000, pos 000b0000 [17:26:51]1162 mmu set 000c0000, pos 000c0000 [17:26:51]1162 mmu set 000d0000, pos 000d0000 [17:26:51]1162 mmu set 000e0000, pos 000e0000 [17:26:51]1162 mmu set 000f0000, pos 000f0000 [17:26:51]1162 mmu set 00100000, pos 00100000 [17:26:51]1162 mmu set 00110000, pos 00110000 [17:26:51]ets Jun 8 2016 00:22:57 [17:26:51] [17:26:51]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:51]configsip: 0, SPIWP:0xee [17:26:51]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:51]mode:QIO, clock div:1 [17:26:51]load:0x3fff0018,len:4 [17:26:51]load:0x928b2121,len:-1725455839 [17:26:51]1162 mmu set 00010000, pos 00010000 [17:26:51]1162 mmu set 00020000, pos 00020000 [17:26:51]1162 mmu set 00030000, pos 00030000 [17:26:51]1162 mmu set 00040000, pos 00040000 [17:26:51]1162 mmu set 00050000, pos 00050000 [17:26:51]1162 mmu set 00060000, pos 00060000 [17:26:51]1162 mmu set 00070000, pos 00070000 [17:26:51]1162 mmu set 00080000, pos 00080000 [17:26:51]1162 mmu set 00090000, pos 00090000 [17:26:51]1162 mmu set 000a0000, pos 000a0000 [17:26:51]1162 mmu set 000b0000, pos 000b0000 [17:26:51]1162 mmu set 000c0000, pos 000c0000 [17:26:51]1162 mmu set 000d0000, pos 000d0000 [17:26:51]1162 mmu set 000e0000, pos 000e0000 [17:26:51]1162 mmu set 000f0000, pos 000f0000 [17:26:51]1162 mmu set 00100000, pos 00100000 [17:26:51]1162 mmu set 00110000, pos 00110000 [17:26:51]ets Jun 8 2016 00:22:57 [17:26:51] [17:26:51]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:51]configsip: 0, SPIWP:0xee [17:26:51]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:51]mode:QIO, clock div:1 [17:26:51]load:0x3fff0018,len:4 [17:26:51]load:0x928b2121,len:-1725455839 [17:26:51]1162 mmu set 00010000, pos 00010000 [17:26:51]1162 mmu set 00020000, pos 00020000 [17:26:51]1162 mmu set 00030000, pos 00030000 [17:26:51]1162 mmu set 00040000, pos 00040000 [17:26:51]1162 mmu set 00050000, pos 00050000 [17:26:51]1162 mmu set 00060000, pos 00060000 [17:26:52]1162 mmu set 00070000, pos 00070000 [17:26:52]1162 mmu set 00080000, pos 00080000 [17:26:52]1162 mmu set 00090000, pos 00090000 [17:26:52]1162 mmu set 000a0000, pos 000a0000 [17:26:52]1162 mmu set 000b0000, pos 000b0000 [17:26:52]1162 mmu set 000c0000, pos 000c0000 [17:26:52]1162 mmu set 000d0000, pos 000d0000 [17:26:52]1162 mmu set 000e0000, pos 000e0000 [17:26:52]1162 mmu set 000f0000, pos 000f0000 [17:26:52]1162 mmu set 00100000, pos 00100000 [17:26:52]1162 mmu set 00110000, pos 00110000 [17:26:52]ets Jun 8 2016 00:22:57 [17:26:52] [17:26:52]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:52]configsip: 0, SPIWP:0xee [17:26:52]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:52]mode:QIO, clock div:1 [17:26:52]load:0x3fff0018,len:4 [17:26:52]load:0x928b2121,len:-1725455839 [17:26:52]1162 mmu set 00010000, pos 00010000 [17:26:52]1162 mmu set 00020000, pos 00020000 [17:26:52]1162 mmu set 00030000, pos 00030000 [17:26:52]1162 mmu set 00040000, pos 00040000 [17:26:52]1162 mmu set 00050000, pos 00050000 [17:26:52]1162 mmu set 00060000, pos 00060000 [17:26:52]1162 mmu set 00070000, pos 00070000 [17:26:52]1162 mmu set 00080000, pos 00080000 [17:26:52]1162 mmu set 00090000, pos 00090000 [17:26:52]1162 mmu set 000a0000, pos 000a0000 [17:26:52]1162 mmu set 000b0000, pos 000b0000 [17:26:52]1162 mmu set 000c0000, pos 000c0000 [17:26:52]1162 mmu set 000d0000, pos 000d0000 [17:26:52]1162 mmu set 000e0000, pos 000e0000 [17:26:52]1162 mmu set 000f0000, pos 000f0000 [17:26:52]1162 mmu set 00100000, pos 00100000 [17:26:52]1162 mmu set 00110000, pos 00110000 [17:26:52]ets Jun 8 2016 00:22:57 [17:26:52] [17:26:52]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:52]configsip: 0, SPIWP:0xee [17:26:52]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:52]mode:QIO, clock div:1 [17:26:52]load:0x3fff0018,len:4 [17:26:52]load:0x928b2121,len:-1725455839 [17:26:52]1162 mmu set 00010000, pos 00010000 [17:26:52]1162 mmu set 00020000, pos 00020000 [17:26:52]1162 mmu set 00030000, pos 00030000 [17:26:52]1162 mmu set 00040000, pos 00040000 [17:26:52]1162 mmu set 00050000, pos 00050000 [17:26:52]1162 mmu set 00060000, pos 00060000 [17:26:52]1162 mmu set 00070000, pos 00070000 [17:26:52]1162 mmu set 00080000, pos 00080000 [17:26:52]1162 mmu set 00090000, pos 00090000 [17:26:52]1162 mmu set 000a0000, pos 000a0000 [17:26:52]1162 mmu set 000b0000, pos 000b0000 [17:26:52]1162 mmu set 000c0000, pos 000c0000 [17:26:52]1162 mmu set 000d0000, pos 000d0000 [17:26:52]1162 mmu set 000e0000, pos 000e0000 [17:26:52]1162 mmu set 000f0000, pos 000f0000 [17:26:52]1162 mmu set 00100000, pos 00100000 [17:26:52]1162 mmu set 00110000, pos 00110000 [17:26:52]ets Jun 8 2016 00:22:57 [17:26:52] [17:26:52]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:52]configsip: 0, SPIWP:0xee [17:26:52]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:52]mode:QIO, clock div:1 [17:26:52]load:0x3fff0018,len:4 [17:26:52]load:0x928b2121,len:-1725455839 [17:26:53]1162 mmu set 00010000, pos 00010000 [17:26:53]1162 mmu set 00020000, pos 00020000 [17:26:53]1162 mmu set 00030000, pos 00030000 [17:26:53]1162 mmu set 00040000, pos 00040000 [17:26:53]1162 mmu set 00050000, pos 00050000 [17:26:53]1162 mmu set 00060000, pos 00060000 [17:26:53]1162 mmu set 00070000, pos 00070000 [17:26:53]1162 mmu set 00080000, pos 00080000 [17:26:53]1162 mmu set 00090000, pos 00090000 [17:26:53]1162 mmu set 000a0000, pos 000a0000 [17:26:53]1162 mmu set 000b0000, pos 000b0000 [17:26:53]1162 mmu set 000c0000, pos 000c0000 [17:26:53]1162 mmu set 000d0000, pos 000d0000 [17:26:53]1162 mmu set 000e0000, pos 000e0000 [17:26:53]1162 mmu set 000f0000, pos 000f0000 [17:26:53]1162 mmu set 00100000, pos 00100000 [17:26:53]1162 mmu set 00110000, pos 00110000 [17:26:53]ets Jun 8 2016 00:22:57 [17:26:53] [17:26:53]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:53]configsip: 0, SPIWP:0xee [17:26:53]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:53]mode:QIO, clock div:1 [17:26:53]load:0x3fff0018,len:4 [17:26:53]load:0x928b2121,len:-1725455839 [17:26:53]1162 mmu set 00010000, pos 00010000 [17:26:53]1162 mmu set 00020000, pos 00020000 [17:26:53]1162 mmu set 00030000, pos 00030000 [17:26:53]1162 mmu set 00040000, pos 00040000 [17:26:53]1162 mmu set 00050000, pos 00050000 [17:26:53]1162 mmu set 00060000, pos 00060000 [17:26:53]1162 mmu set 00070000, pos 00070000 [17:26:53]1162 mmu set 00080000, pos 00080000 [17:26:53]1162 mmu set 00090000, pos 00090000 [17:26:53]1162 mmu set 000a0000, pos 000a0000 [17:26:53]1162 mmu set 000b0000, pos 000b0000 [17:26:53]1162 mmu set 000c0000, pos 000c0000 [17:26:53]1162 mmu set 000d0000, pos 000d0000 [17:26:53]1162 mmu set 000e0000, pos 000e0000 [17:26:53]1162 mmu set 000f0000, pos 000f0000 [17:26:53]1162 mmu set 00100000, pos 00100000 [17:26:53]1162 mmu set 00110000, pos 00110000 [17:26:53]ets Jun 8 2016 00:22:57 [17:26:53] [17:26:53]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:53]configsip: 0, SPIWP:0xee [17:26:53]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:53]mode:QIO, clock div:1 [17:26:53]load:0x3fff0018,len:4 [17:26:53]load:0x928b2121,len:-1725455839 [17:26:53]1162 mmu set 00010000, pos 00010000 [17:26:53]1162 mmu set 00020000, pos 00020000 [17:26:53]1162 mmu set 00030000, pos 00030000 [17:26:53]1162 mmu set 00040000, pos 00040000 [17:26:53]1162 mmu set 00050000, pos 00050000 [17:26:53]1162 mmu set 00060000, pos 00060000 [17:26:53]1162 mmu set 00070000, pos 00070000 [17:26:53]1162 mmu set 00080000, pos 00080000 [17:26:53]1162 mmu set 00090000, pos 00090000 [17:26:53]1162 mmu set 000a0000, pos 000a0000 [17:26:53]1162 mmu set 000b0000, pos 000b0000 [17:26:53]1162 mmu set 000c0000, pos 000c0000 [17:26:53]1162 mmu set 000d0000, pos 000d0000 [17:26:54]1162 mmu set 000e0000, pos 000e0000 [17:26:54]1162 mmu set 000f0000, pos 000f0000 [17:26:54]1162 mmu set 00100000, pos 00100000 [17:26:54]1162 mmu set 00110000, pos 00110000 [17:26:54]ets Jun 8 2016 00:22:57 [17:26:54] [17:26:54]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:54]configsip: 0, SPIWP:0xee [17:26:54]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:54]mode:QIO, clock div:1 [17:26:54]load:0x3fff0018,len:4 [17:26:54]load:0x928b2121,len:-1725455839 [17:26:54]1162 mmu set 00010000, pos 00010000 [17:26:54]1162 mmu set 00020000, pos 00020000 [17:26:54]1162 mmu set 00030000, pos 00030000 [17:26:54]1162 mmu set 00040000, pos 00040000 [17:26:54]1162 mmu set 00050000, pos 00050000 [17:26:54]1162 mmu set 00060000, pos 00060000 [17:26:54]1162 mmu set 00070000, pos 00070000 [17:26:54]1162 mmu set 00080000, pos 00080000 [17:26:54]1162 mmu set 00090000, pos 00090000 [17:26:54]1162 mmu set 000a0000, pos 000a0000 [17:26:54]1162 mmu set 000b0000, pos 000b0000 [17:26:54]1162 mmu set 000c0000, pos 000c0000 [17:26:54]1162 mmu set 000d0000, pos 000d0000 [17:26:54]1162 mmu set 000e0000, pos 000e0000 [17:26:54]1162 mmu set 000f0000, pos 000f0000 [17:26:54]1162 mmu set 00100000, pos 00100000 [17:26:54]1162 mmu set 00110000, pos 00110000 [17:26:54]ets Jun 8 2016 00:22:57 [17:26:54] [17:26:54]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:54]configsip: 0, SPIWP:0xee [17:26:54]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:54]mode:QIO, clock div:1 [17:26:54]load:0x3fff0018,len:4 [17:26:54]load:0x928b2121,len:-1725455839 [17:26:54]1162 mmu set 00010000, pos 00010000 [17:26:54]1162 mmu set 00020000, pos 00020000 [17:26:54]1162 mmu set 00030000, pos 00030000 [17:26:54]1162 mmu set 00040000, pos 00040000 [17:26:54]1162 mmu set 00050000, pos 00050000 [17:26:54]1162 mmu set 00060000, pos 00060000 [17:26:54]1162 mmu set 00070000, pos 00070000 [17:26:54]1162 mmu set 00080000, pos 00080000 [17:26:54]1162 mmu set 00090000, pos 00090000 [17:26:54]1162 mmu set 000a0000, pos 000a0000 [17:26:54]1162 mmu set 000b0000, pos 000b0000 [17:26:54]1162 mmu set 000c0000, pos 000c0000 [17:26:54]1162 mmu set 000d0000, pos 000d0000 [17:26:54]1162 mmu set 000e0000, pos 000e0000 [17:26:54]1162 mmu set 000f0000, pos 000f0000 [17:26:54]1162 mmu set 00100000, pos 00100000 [17:26:54]1162 mmu set 00110000, pos 00110000 [17:26:54]ets Jun 8 2016 00:22:57 [17:26:54] [17:26:54]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:54]configsip: 0, SPIWP:0xee [17:26:54]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:54]mode:QIO, clock div:1 [17:26:54]load:0x3fff0018,len:4 [17:26:54]load:0x928b2121,len:-1725455839 [17:26:54]1162 mmu set 00010000, pos 00010000 [17:26:54]1162 mmu set 00020000, pos 00020000 [17:26:54]1162 mmu set 00030000, pos 00030000 [17:26:54]1162 mmu set 00040000, pos 00040000 [17:26:54]1162 mmu set 00050000, pos 00050000 [17:26:54]1162 mmu set 00060000, pos 00060000 [17:26:54]1162 mmu set 00070000, pos 00070000 [17:26:54]1162 mmu set 00080000, pos 00080000 [17:26:55]1162 mmu set 00090000, pos 00090000 [17:26:55]1162 mmu set 000a0000, pos 000a0000 [17:26:55]1162 mmu set 000b0000, pos 000b0000 [17:26:55]1162 mmu set 000c0000, pos 000c0000 [17:26:55]1162 mmu set 000d0000, pos 000d0000 [17:26:55]1162 mmu set 000e0000, pos 000e0000 [17:26:55]1162 mmu set 000f0000, pos 000f0000 [17:26:55]1162 mmu set 00100000, pos 00100000 [17:26:55]1162 mmu set 00110000, pos 00110000 [17:26:55]ets Jun 8 2016 00:22:57 [17:26:55] [17:26:55]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:55]configsip: 0, SPIWP:0xee [17:26:55]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:55]mode:QIO, clock div:1 [17:26:55]load:0x3fff0018,len:4 [17:26:55]load:0x928b2121,len:-1725455839 [17:26:55]1162 mmu set 00010000, pos 00010000 [17:26:55]1162 mmu set 00020000, pos 00020000 [17:26:55]1162 mmu set 00030000, pos 00030000 [17:26:55]1162 mmu set 00040000, pos 00040000 [17:26:55]1162 mmu set 00050000, pos 00050000 [17:26:55]1162 mmu set 00060000, pos 00060000 [17:26:55]1162 mmu set 00070000, pos 00070000 [17:26:55]1162 mmu set 00080000, pos 00080000 [17:26:55]1162 mmu set 00090000, pos 00090000 [17:26:55]1162 mmu set 000a0000, pos 000a0000 [17:26:55]1162 mmu set 000b0000, pos 000b0000 [17:26:55]1162 mmu set 000c0000, pos 000c0000 [17:26:55]1162 mmu set 000d0000, pos 000d0000 [17:26:55]1162 mmu set 000e0000, pos 000e0000 [17:26:55]1162 mmu set 000f0000, pos 000f0000 [17:26:55]1162 mmu set 00100000, pos 00100000 [17:26:55]1162 mmu set 00110000, pos 00110000 [17:26:55]ets Jun 8 2016 00:22:57 [17:26:55] [17:26:55]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:55]configsip: 0, SPIWP:0xee [17:26:55]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:55]mode:QIO, clock div:1 [17:26:55]load:0x3fff0018,len:4 [17:26:55]load:0x928b2121,len:-1725455839 [17:26:55]1162 mmu set 00010000, pos 00010000 [17:26:55]1162 mmu set 00020000, pos 00020000 [17:26:55]1162 mmu set 00030000, pos 00030000 [17:26:55]1162 mmu set 00040000, pos 00040000 [17:26:55]1162 mmu set 00050000, pos 00050000 [17:26:55]1162 mmu set 00060000, pos 00060000 [17:26:55]1162 mmu set 00070000, pos 00070000 [17:26:55]1162 mmu set 00080000, pos 00080000 [17:26:55]1162 mmu set 00090000, pos 00090000 [17:26:55]1162 mmu set 000a0000, pos 000a0000 [17:26:55]1162 mmu set 000b0000, pos 000b0000 [17:26:55]1162 mmu set 000c0000, pos 000c0000 [17:26:55]1162 mmu set 000d0000, pos 000d0000 [17:26:55]1162 mmu set 000e0000, pos 000e0000 [17:26:55]1162 mmu set 000f0000, pos 000f0000 [17:26:55]1162 mmu set 00100000, pos 00100000 [17:26:55]1162 mmu set 00110000, pos 00110000 [17:26:55]ets Jun 8 2016 00:22:57 [17:26:55] [17:26:55]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:55]configsip: 0, SPIWP:0xee [17:26:55]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:55]mode:QIO, clock div:1 [17:26:55]load:0x3fff0018,len:4 [17:26:55]load:0x928b2121,len:-1725455839 [17:26:55]1162 mmu set 00010000, pos 00010000 [17:26:55]1162 mmu set 00020000, pos 00020000 [17:26:55]1162 mmu set 00030000, pos 00030000 [17:26:56]1162 mmu set 00040000, pos 00040000 [17:26:56]1162 mmu set 00050000, pos 00050000 [17:26:56]1162 mmu set 00060000, pos 00060000 [17:26:56]1162 mmu set 00070000, pos 00070000 [17:26:56]1162 mmu set 00080000, pos 00080000 [17:26:56]1162 mmu set 00090000, pos 00090000 [17:26:56]1162 mmu set 000a0000, pos 000a0000 [17:26:56]1162 mmu set 000b0000, pos 000b0000 [17:26:56]1162 mmu set 000c0000, pos 000c0000 [17:26:56]1162 mmu set 000d0000, pos 000d0000 [17:26:56]1162 mmu set 000e0000, pos 000e0000 [17:26:56]1162 mmu set 000f0000, pos 000f0000 [17:26:56]1162 mmu set 00100000, pos 00100000 [17:26:56]1162 mmu set 00110000, pos 00110000 [17:26:56]ets Jun 8 2016 00:22:57 [17:26:56] [17:26:56]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:56]configsip: 0, SPIWP:0xee [17:26:56]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:56]mode:QIO, clock div:1 [17:26:56]load:0x3fff0018,len:4 [17:26:56]load:0x928b2121,len:-1725455839 [17:26:56]1162 mmu set 00010000, pos 00010000 [17:26:56]1162 mmu set 00020000, pos 00020000 [17:26:56]1162 mmu set 00030000, pos 00030000 [17:26:56]1162 mmu set 00040000, pos 00040000 [17:26:56]1162 mmu set 00050000, pos 00050000 [17:26:56]1162 mmu set 00060000, pos 00060000 [17:26:56]1162 mmu set 00070000, pos 00070000 [17:26:56]1162 mmu set 00080000, pos 00080000 [17:26:56]1162 mmu set 00090000, pos 00090000 [17:26:56]1162 mmu set 000a0000, pos 000a0000 [17:26:56]1162 mmu set 000b0000, pos 000b0000 [17:26:56]1162 mmu set 000c0000, pos 000c0000 [17:26:56]1162 mmu set 000d0000, pos 000d0000 [17:26:56]1162 mmu set 000e0000, pos 000e0000 [17:26:56]1162 mmu set 000f0000, pos 000f0000 [17:26:56]1162 mmu set 00100000, pos 00100000 [17:26:56]1162 mmu set 00110000, pos 00110000 [17:26:56]ets Jun 8 2016 00:22:57 [17:26:56] [17:26:56]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:56]configsip: 0, SPIWP:0xee [17:26:56]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:56]mode:QIO, clock div:1 [17:26:56]load:0x3fff0018,len:4 [17:26:56]load:0x928b2121,len:-1725455839 [17:26:56]1162 mmu set 00010000, pos 00010000 [17:26:56]1162 mmu set 00020000, pos 00020000 [17:26:56]1162 mmu set 00030000, pos 00030000 [17:26:56]1162 mmu set 00040000, pos 00040000 [17:26:56]1162 mmu set 00050000, pos 00050000 [17:26:56]1162 mmu set 00060000, pos 00060000 [17:26:56]1162 mmu set 00070000, pos 00070000 [17:26:56]1162 mmu set 00080000, pos 00080000 [17:26:56]1162 mmu set 00090000, pos 00090000 [17:26:56]1162 mmu set 000a0000, pos 000a0000 [17:26:56]1162 mmu set 000b0000, pos 000b0000 [17:26:56]1162 mmu set 000c0000, pos 000c0000 [17:26:56]1162 mmu set 000d0000, pos 000d0000 [17:26:56]1162 mmu set 000e0000, pos 000e0000 [17:26:56]1162 mmu set 000f0000, pos 000f0000 [17:26:56]1162 mmu set 00100000, pos 00100000 [17:26:57]1162 mmu set 00110000, pos 00110000 [17:26:57]ets Jun 8 2016 00:22:57 [17:26:57] [17:26:57]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:57]configsip: 0, SPIWP:0xee [17:26:57]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:57]mode:QIO, clock div:1 [17:26:57]load:0x3fff0018,len:4 [17:26:57]load:0x928b2121,len:-1725455839 [17:26:57]1162 mmu set 00010000, pos 00010000 [17:26:57]1162 mmu set 00020000, pos 00020000 [17:26:57]1162 mmu set 00030000, pos 00030000 [17:26:57]1162 mmu set 00040000, pos 00040000 [17:26:57]1162 mmu set 00050000, pos 00050000 [17:26:57]1162 mmu set 00060000, pos 00060000 [17:26:57]1162 mmu set 00070000, pos 00070000 [17:26:57]1162 mmu set 00080000, pos 00080000 [17:26:57]1162 mmu set 00090000, pos 00090000 [17:26:57]1162 mmu set 000a0000, pos 000a0000 [17:26:57]1162 mmu set 000b0000, pos 000b0000 [17:26:57]1162 mmu set 000c0000, pos 000c0000 [17:26:57]1162 mmu set 000d0000, pos 000d0000 [17:26:57]1162 mmu set 000e0000, pos 000e0000 [17:26:57]1162 mmu set 000f0000, pos 000f0000 [17:26:57]1162 mmu set 00100000, pos 00100000 [17:26:57]1162 mmu set 00110000, pos 00110000 [17:26:57]ets Jun 8 2016 00:22:57 [17:26:57] [17:26:57]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:57]configsip: 0, SPIWP:0xee [17:26:57]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:57]mode:QIO, clock div:1 [17:26:57]load:0x3fff0018,len:4 [17:26:57]load:0x928b2121,len:-1725455839 [17:26:57]1162 mmu set 00010000, pos 00010000 [17:26:57]1162 mmu set 00020000, pos 00020000 [17:26:57]1162 mmu set 00030000, pos 00030000 [17:26:57]1162 mmu set 00040000, pos 00040000 [17:26:57]1162 mmu set 00050000, pos 00050000 [17:26:57]1162 mmu set 00060000, pos 00060000 [17:26:57]1162 mmu set 00070000, pos 00070000 [17:26:57]1162 mmu set 00080000, pos 00080000 [17:26:57]1162 mmu set 00090000, pos 00090000 [17:26:57]1162 mmu set 000a0000, pos 000a0000 [17:26:57]1162 mmu set 000b0000, pos 000b0000 [17:26:57]1162 mmu set 000c0000, pos 000c0000 [17:26:57]1162 mmu set 000d0000, pos 000d0000 [17:26:57]1162 mmu set 000e0000, pos 000e0000 [17:26:57]1162 mmu set 000f0000, pos 000f0000 [17:26:57]1162 mmu set 00100000, pos 00100000 [17:26:57]1162 mmu set 00110000, pos 00110000 [17:26:57]ets Jun 8 2016 00:22:57 [17:26:57] [17:26:57]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:57]configsip: 0, SPIWP:0xee [17:26:57]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:57]mode:QIO, clock div:1 [17:26:57]load:0x3fff0018,len:4 [17:26:57]load:0x928b2121,len:-1725455839 [17:26:57]1162 mmu set 00010000, pos 00010000 [17:26:57]1162 mmu set 00020000, pos 00020000 [17:26:57]1162 mmu set 00030000, pos 00030000 [17:26:57]1162 mmu set 00040000, pos 00040000 [17:26:57]1162 mmu set 00050000, pos 00050000 [17:26:57]1162 mmu set 00060000, pos 00060000 [17:26:57]1162 mmu set 00070000, pos 00070000 [17:26:57]1162 mmu set 00080000, pos 00080000 [17:26:57]1162 mmu set 00090000, pos 00090000 [17:26:57]1162 mmu set 000a0000, pos 000a0000 [17:26:58]1162 mmu set 000b0000, pos 000b0000 [17:26:58]1162 mmu set 000c0000, pos 000c0000 [17:26:58]1162 mmu set 000d0000, pos 000d0000 [17:26:58]1162 mmu set 000e0000, pos 000e0000 [17:26:58]1162 mmu set 000f0000, pos 000f0000 [17:26:58]1162 mmu set 00100000, pos 00100000 [17:26:58]1162 mmu set 00110000, pos 00110000 [17:26:58]ets Jun 8 2016 00:22:57 [17:26:58] [17:26:58]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:58]configsip: 0, SPIWP:0xee [17:26:58]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:58]mode:QIO, clock div:1 [17:26:58]load:0x3fff0018,len:4 [17:26:58]load:0x928b2121,len:-1725455839 [17:26:58]1162 mmu set 00010000, pos 00010000 [17:26:58]1162 mmu set 00020000, pos 00020000 [17:26:58]1162 mmu set 00030000, pos 00030000 [17:26:58]1162 mmu set 00040000, pos 00040000 [17:26:58]1162 mmu set 00050000, pos 00050000 [17:26:58]1162 mmu set 00060000, pos 00060000 [17:26:58]1162 mmu set 00070000, pos 00070000 [17:26:58]1162 mmu set 00080000, pos 00080000 [17:26:58]1162 mmu set 00090000, pos 00090000 [17:26:58]1162 mmu set 000a0000, pos 000a0000 [17:26:58]1162 mmu set 000b0000, pos 000b0000 [17:26:58]1162 mmu set 000c0000, pos 000c0000 [17:26:58]1162 mmu set 000d0000, pos 000d0000 [17:26:58]1162 mmu set 000e0000, pos 000e0000 [17:26:58]1162 mmu set 000f0000, pos 000f0000 [17:26:58]1162 mmu set 00100000, pos 00100000 [17:26:58]1162 mmu set 00110000, pos 00110000 [17:26:58]ets Jun 8 2016 00:22:57 [17:26:58] [17:26:58]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:58]configsip: 0, SPIWP:0xee [17:26:58]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:58]mode:QIO, clock div:1 [17:26:58]load:0x3fff0018,len:4 [17:26:58]load:0x928b2121,len:-1725455839 [17:26:58]1162 mmu set 00010000, pos 00010000 [17:26:58]1162 mmu set 00020000, pos 00020000 [17:26:58]1162 mmu set 00030000, pos 00030000 [17:26:58]1162 mmu set 00040000, pos 00040000 [17:26:58]1162 mmu set 00050000, pos 00050000 [17:26:58]1162 mmu set 00060000, pos 00060000 [17:26:58]1162 mmu set 00070000, pos 00070000 [17:26:58]1162 mmu set 00080000, pos 00080000 [17:26:58]1162 mmu set 00090000, pos 00090000 [17:26:58]1162 mmu set 000a0000, pos 000a0000 [17:26:58]1162 mmu set 000b0000, pos 000b0000 [17:26:58]1162 mmu set 000c0000, pos 000c0000 [17:26:58]1162 mmu set 000d0000, pos 000d0000 [17:26:58]1162 mmu set 000e0000, pos 000e0000 [17:26:58]1162 mmu set 000f0000, pos 000f0000 [17:26:58]1162 mmu set 00100000, pos 00100000 [17:26:58]1162 mmu set 00110000, pos 00110000 [17:26:58]ets Jun 8 2016 00:22:57 [17:26:58] [17:26:58]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:58]configsip: 0, SPIWP:0xee [17:26:58]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:58]mode:QIO, clock div:1 [17:26:58]load:0x3fff0018,len:4 [17:26:58]load:0x928b2121,len:-1725455839 [17:26:58]1162 mmu set 00010000, pos 00010000 [17:26:58]1162 mmu set 00020000, pos 00020000 [17:26:58]1162 mmu set 00030000, pos 00030000 [17:26:58]1162 mmu set 00040000, pos 00040000 [17:26:58]1162 mmu set 00050000, pos 00050000 [17:26:59]1162 mmu set 00060000, pos 00060000 [17:26:59]1162 mmu set 00070000, pos 00070000 [17:26:59]1162 mmu set 00080000, pos 00080000 [17:26:59]1162 mmu set 00090000, pos 00090000 [17:26:59]1162 mmu set 000a0000, pos 000a0000 [17:26:59]1162 mmu set 000b0000, pos 000b0000 [17:26:59]1162 mmu set 000c0000, pos 000c0000 [17:26:59]1162 mmu set 000d0000, pos 000d0000 [17:26:59]1162 mmu set 000e0000, pos 000e0000 [17:26:59]1162 mmu set 000f0000, pos 000f0000 [17:26:59]1162 mmu set 00100000, pos 00100000 [17:26:59]1162 mmu set 00110000, pos 00110000 [17:26:59]ets Jun 8 2016 00:22:57 [17:26:59] [17:26:59]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:59]configsip: 0, SPIWP:0xee [17:26:59]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:59]mode:QIO, clock div:1 [17:26:59]load:0x3fff0018,len:4 [17:26:59]load:0x928b2121,len:-1725455839 [17:26:59]1162 mmu set 00010000, pos 00010000 [17:26:59]1162 mmu set 00020000, pos 00020000 [17:26:59]1162 mmu set 00030000, pos 00030000 [17:26:59]1162 mmu set 00040000, pos 00040000 [17:26:59]1162 mmu set 00050000, pos 00050000 [17:26:59]1162 mmu set 00060000, pos 00060000 [17:26:59]1162 mmu set 00070000, pos 00070000 [17:26:59]1162 mmu set 00080000, pos 00080000 [17:26:59]1162 mmu set 00090000, pos 00090000 [17:26:59]1162 mmu set 000a0000, pos 000a0000 [17:26:59]1162 mmu set 000b0000, pos 000b0000 [17:26:59]1162 mmu set 000c0000, pos 000c0000 [17:26:59]1162 mmu set 000d0000, pos 000d0000 [17:26:59]1162 mmu set 000e0000, pos 000e0000 [17:26:59]1162 mmu set 000f0000, pos 000f0000 [17:26:59]1162 mmu set 00100000, pos 00100000 [17:26:59]1162 mmu set 00110000, pos 00110000 [17:26:59]ets Jun 8 2016 00:22:57 [17:26:59] [17:26:59]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:59]configsip: 0, SPIWP:0xee [17:26:59]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:59]mode:QIO, clock div:1 [17:26:59]load:0x3fff0018,len:4 [17:26:59]load:0x928b2121,len:-1725455839 [17:26:59]1162 mmu set 00010000, pos 00010000 [17:26:59]1162 mmu set 00020000, pos 00020000 [17:26:59]1162 mmu set 00030000, pos 00030000 [17:26:59]1162 mmu set 00040000, pos 00040000 [17:26:59]1162 mmu set 00050000, pos 00050000 [17:26:59]1162 mmu set 00060000, pos 00060000 [17:26:59]1162 mmu set 00070000, pos 00070000 [17:26:59]1162 mmu set 00080000, pos 00080000 [17:26:59]1162 mmu set 00090000, pos 00090000 [17:26:59]1162 mmu set 000a0000, pos 000a0000 [17:26:59]1162 mmu set 000b0000, pos 000b0000 [17:26:59]1162 mmu set 000c0000, pos 000c0000 [17:26:59]1162 mmu set 000d0000, pos 000d0000 [17:26:59]1162 mmu set 000e0000, pos 000e0000 [17:26:59]1162 mmu set 000f0000, pos 000f0000 [17:26:59]1162 mmu set 00100000, pos 00100000 [17:26:59]1162 mmu set 00110000, pos 00110000 [17:26:59]ets Jun 8 2016 00:22:57 [17:26:59] [17:26:59]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:26:59]configsip: 0, SPIWP:0xee [17:26:59]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:26:59]mode:QIO, clock div:1 [17:27:00]load:0x3fff0018,len:4 [17:27:00]load:0x928b2121,len:-1725455839 [17:27:00]1162 mmu set 00010000, pos 00010000 [17:27:00]1162 mmu set 00020000, pos 00020000 [17:27:00]1162 mmu set 00030000, pos 00030000 [17:27:00]1162 mmu set 00040000, pos 00040000 [17:27:00]1162 mmu set 00050000, pos 00050000 [17:27:00]1162 mmu set 00060000, pos 00060000 [17:27:00]1162 mmu set 00070000, pos 00070000 [17:27:00]1162 mmu set 00080000, pos 00080000 [17:27:00]1162 mmu set 00090000, pos 00090000 [17:27:00]1162 mmu set 000a0000, pos 000a0000 [17:27:00]1162 mmu set 000b0000, pos 000b0000 [17:27:00]1162 mmu set 000c0000, pos 000c0000 [17:27:00]1162 mmu set 000d0000, pos 000d0000 [17:27:00]1162 mmu set 000e0000, pos 000e0000 [17:27:00]1162 mmu set 000f0000, pos 000f0000 [17:27:00]1162 mmu set 00100000, pos 00100000 [17:27:00]1162 mmu set 00110000, pos 00110000 [17:27:00]ets Jun 8 2016 00:22:57 [17:27:00] [17:27:00]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:00]configsip: 0, SPIWP:0xee [17:27:00]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:00]mode:QIO, clock div:1 [17:27:00]load:0x3fff0018,len:4 [17:27:00]load:0x928b2121,len:-1725455839 [17:27:00]1162 mmu set 00010000, pos 00010000 [17:27:00]1162 mmu set 00020000, pos 00020000 [17:27:00]1162 mmu set 00030000, pos 00030000 [17:27:00]1162 mmu set 00040000, pos 00040000 [17:27:00]1162 mmu set 00050000, pos 00050000 [17:27:00]1162 mmu set 00060000, pos 00060000 [17:27:00]1162 mmu set 00070000, pos 00070000 [17:27:00]1162 mmu set 00080000, pos 00080000 [17:27:00]1162 mmu set 00090000, pos 00090000 [17:27:00]1162 mmu set 000a0000, pos 000a0000 [17:27:00]1162 mmu set 000b0000, pos 000b0000 [17:27:00]1162 mmu set 000c0000, pos 000c0000 [17:27:00]1162 mmu set 000d0000, pos 000d0000 [17:27:00]1162 mmu set 000e0000, pos 000e0000 [17:27:00]1162 mmu set 000f0000, pos 000f0000 [17:27:00]1162 mmu set 00100000, pos 00100000 [17:27:00]1162 mmu set 00110000, pos 00110000 [17:27:00]ets Jun 8 2016 00:22:57 [17:27:00] [17:27:00]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:00]configsip: 0, SPIWP:0xee [17:27:00]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:00]mode:QIO, clock div:1 [17:27:00]load:0x3fff0018,len:4 [17:27:00]load:0x928b2121,len:-1725455839 [17:27:00]1162 mmu set 00010000, pos 00010000 [17:27:00]1162 mmu set 00020000, pos 00020000 [17:27:00]1162 mmu set 00030000, pos 00030000 [17:27:00]1162 mmu set 00040000, pos 00040000 [17:27:00]1162 mmu set 00050000, pos 00050000 [17:27:00]1162 mmu set 00060000, pos 00060000 [17:27:00]1162 mmu set 00070000, pos 00070000 [17:27:00]1162 mmu set 00080000, pos 00080000 [17:27:00]1162 mmu set 00090000, pos 00090000 [17:27:00]1162 mmu set 000a0000, pos 000a0000 [17:27:00]1162 mmu set 000b0000, pos 000b0000 [17:27:00]1162 mmu set 000c0000, pos 000c0000 [17:27:00]1162 mmu set 000d0000, pos 000d0000 [17:27:01]1162 mmu set 000e0000, pos 000e0000 [17:27:01]1162 mmu set 000f0000, pos 000f0000 [17:27:01]1162 mmu set 00100000, pos 00100000 [17:27:01]1162 mmu set 00110000, pos 00110000 [17:27:01]ets Jun 8 2016 00:22:57 [17:27:01] [17:27:01]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:01]configsip: 0, SPIWP:0xee [17:27:01]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:01]mode:QIO, clock div:1 [17:27:01]load:0x3fff0018,len:4 [17:27:01]load:0x928b2121,len:-1725455839 [17:27:01]1162 mmu set 00010000, pos 00010000 [17:27:01]1162 mmu set 00020000, pos 00020000 [17:27:01]1162 mmu set 00030000, pos 00030000 [17:27:01]1162 mmu set 00040000, pos 00040000 [17:27:01]1162 mmu set 00050000, pos 00050000 [17:27:01]1162 mmu set 00060000, pos 00060000 [17:27:01]1162 mmu set 00070000, pos 00070000 [17:27:01]1162 mmu set 00080000, pos 00080000 [17:27:01]1162 mmu set 00090000, pos 00090000 [17:27:01]1162 mmu set 000a0000, pos 000a0000 [17:27:01]1162 mmu set 000b0000, pos 000b0000 [17:27:01]1162 mmu set 000c0000, pos 000c0000 [17:27:01]1162 mmu set 000d0000, pos 000d0000 [17:27:01]1162 mmu set 000e0000, pos 000e0000 [17:27:01]1162 mmu set 000f0000, pos 000f0000 [17:27:01]1162 mmu set 00100000, pos 00100000 [17:27:01]1162 mmu set 00110000, pos 00110000 [17:27:01]ets Jun 8 2016 00:22:57 [17:27:01] [17:27:01]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:01]configsip: 0, SPIWP:0xee [17:27:01]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:01]mode:QIO, clock div:1 [17:27:01]load:0x3fff0018,len:4 [17:27:01]load:0x928b2121,len:-1725455839 [17:27:01]1162 mmu set 00010000, pos 00010000 [17:27:01]1162 mmu set 00020000, pos 00020000 [17:27:01]1162 mmu set 00030000, pos 00030000 [17:27:01]1162 mmu set 00040000, pos 00040000 [17:27:01]1162 mmu set 00050000, pos 00050000 [17:27:01]1162 mmu set 00060000, pos 00060000 [17:27:01]1162 mmu set 00070000, pos 00070000 [17:27:01]1162 mmu set 00080000, pos 00080000 [17:27:01]1162 mmu set 00090000, pos 00090000 [17:27:01]1162 mmu set 000a0000, pos 000a0000 [17:27:01]1162 mmu set 000b0000, pos 000b0000 [17:27:01]1162 mmu set 000c0000, pos 000c0000 [17:27:01]1162 mmu set 000d0000, pos 000d0000 [17:27:01]1162 mmu set 000e0000, pos 000e0000 [17:27:01]1162 mmu set 000f0000, pos 000f0000 [17:27:01]1162 mmu set 00100000, pos 00100000 [17:27:01]1162 mmu set 00110000, pos 00110000 [17:27:01]ets Jun 8 2016 00:22:57 [17:27:01] [17:27:01]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:01]configsip: 0, SPIWP:0xee [17:27:01]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:01]mode:QIO, clock div:1 [17:27:01]load:0x3fff0018,len:4 [17:27:01]load:0x928b2121,len:-1725455839 [17:27:01]1162 mmu set 00010000, pos 00010000 [17:27:01]1162 mmu set 00020000, pos 00020000 [17:27:01]1162 mmu set 00030000, pos 00030000 [17:27:01]1162 mmu set 00040000, pos 00040000 [17:27:01]1162 mmu set 00050000, pos 00050000 [17:27:01]1162 mmu set 00060000, pos 00060000 [17:27:01]1162 mmu set 00070000, pos 00070000 [17:27:02]1162 mmu set 00080000, pos 00080000 [17:27:02]1162 mmu set 00090000, pos 00090000 [17:27:02]1162 mmu set 000a0000, pos 000a0000 [17:27:02]1162 mmu set 000b0000, pos 000b0000 [17:27:02]1162 mmu set 000c0000, pos 000c0000 [17:27:02]1162 mmu set 000d0000, pos 000d0000 [17:27:02]1162 mmu set 000e0000, pos 000e0000 [17:27:02]1162 mmu set 000f0000, pos 000f0000 [17:27:02]1162 mmu set 00100000, pos 00100000 [17:27:02]1162 mmu set 00110000, pos 00110000 [17:27:02]ets Jun 8 2016 00:22:57 [17:27:02] [17:27:02]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:02]configsip: 0, SPIWP:0xee [17:27:02]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:02]mode:QIO, clock div:1 [17:27:02]load:0x3fff0018,len:4 [17:27:02]load:0x928b2121,len:-1725455839 [17:27:02]1162 mmu set 00010000, pos 00010000 [17:27:02]1162 mmu set 00020000, pos 00020000 [17:27:02]1162 mmu set 00030000, pos 00030000 [17:27:02]1162 mmu set 00040000, pos 00040000 [17:27:02]1162 mmu set 00050000, pos 00050000 [17:27:02]1162 mmu set 00060000, pos 00060000 [17:27:02]1162 mmu set 00070000, pos 00070000 [17:27:02]1162 mmu set 00080000, pos 00080000 [17:27:02]1162 mmu set 00090000, pos 00090000 [17:27:02]1162 mmu set 000a0000, pos 000a0000 [17:27:02]1162 mmu set 000b0000, pos 000b0000 [17:27:02]1162 mmu set 000c0000, pos 000c0000 [17:27:02]1162 mmu set 000d0000, pos 000d0000 [17:27:02]1162 mmu set 000e0000, pos 000e0000 [17:27:02]1162 mmu set 000f0000, pos 000f0000 [17:27:02]1162 mmu set 00100000, pos 00100000 [17:27:02]1162 mmu set 00110000, pos 00110000 [17:27:02]ets Jun 8 2016 00:22:57 [17:27:02] [17:27:02]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:02]configsip: 0, SPIWP:0xee [17:27:02]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:02]mode:QIO, clock div:1 [17:27:02]load:0x3fff0018,len:4 [17:27:02]load:0x928b2121,len:-1725455839 [17:27:02]1162 mmu set 00010000, pos 00010000 [17:27:02]1162 mmu set 00020000, pos 00020000 [17:27:02]1162 mmu set 00030000, pos 00030000 [17:27:02]1162 mmu set 00040000, pos 00040000 [17:27:02]1162 mmu set 00050000, pos 00050000 [17:27:02]1162 mmu set 00060000, pos 00060000 [17:27:02]1162 mmu set 00070000, pos 00070000 [17:27:02]1162 mmu set 00080000, pos 00080000 [17:27:02]1162 mmu set 00090000, pos 00090000 [17:27:02]1162 mmu set 000a0000, pos 000a0000 [17:27:02]1162 mmu set 000b0000, pos 000b0000 [17:27:02]1162 mmu set 000c0000, pos 000c0000 [17:27:02]1162 mmu set 000d0000, pos 000d0000 [17:27:02]1162 mmu set 000e0000, pos 000e0000 [17:27:02]1162 mmu set 000f0000, pos 000f0000 [17:27:02]1162 mmu set 00100000, pos 00100000 [17:27:02]1162 mmu set 00110000, pos 00110000 [17:27:02]ets Jun 8 2016 00:22:57 [17:27:02] [17:27:02]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:02]configsip: 0, SPIWP:0xee [17:27:02]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:02]mode:QIO, clock div:1 [17:27:02]load:0x3fff0018,len:4 [17:27:02]load:0x928b2121,len:-1725455839 [17:27:02]1162 mmu set 00010000, pos 00010000 [17:27:02]1162 mmu set 00020000, pos 00020000 [17:27:03]1162 mmu set 00030000, pos 00030000 [17:27:03]1162 mmu set 00040000, pos 00040000 [17:27:03]1162 mmu set 00050000, pos 00050000 [17:27:03]1162 mmu set 00060000, pos 00060000 [17:27:03]1162 mmu set 00070000, pos 00070000 [17:27:03]1162 mmu set 00080000, pos 00080000 [17:27:03]1162 mmu set 00090000, pos 00090000 [17:27:03]1162 mmu set 000a0000, pos 000a0000 [17:27:03]1162 mmu set 000b0000, pos 000b0000 [17:27:03]1162 mmu set 000c0000, pos 000c0000 [17:27:03]1162 mmu set 000d0000, pos 000d0000 [17:27:03]1162 mmu set 000e0000, pos 000e0000 [17:27:03]1162 mmu set 000f0000, pos 000f0000 [17:27:03]1162 mmu set 00100000, pos 00100000 [17:27:03]1162 mmu set 00110000, pos 00110000 [17:27:03]ets Jun 8 2016 00:22:57 [17:27:03] [17:27:03]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:03]configsip: 0, SPIWP:0xee [17:27:03]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:03]mode:QIO, clock div:1 [17:27:03]load:0x3fff0018,len:4 [17:27:03]load:0x928b2121,len:-1725455839 [17:27:03]1162 mmu set 00010000, pos 00010000 [17:27:03]1162 mmu set 00020000, pos 00020000 [17:27:03]1162 mmu set 00030000, pos 00030000 [17:27:03]1162 mmu set 00040000, pos 00040000 [17:27:03]1162 mmu set 00050000, pos 00050000 [17:27:03]1162 mmu set 00060000, pos 00060000 [17:27:03]1162 mmu set 00070000, pos 00070000 [17:27:03]1162 mmu set 00080000, pos 00080000 [17:27:03]1162 mmu set 00090000, pos 00090000 [17:27:03]1162 mmu set 000a0000, pos 000a0000 [17:27:03]1162 mmu set 000b0000, pos 000b0000 [17:27:03]1162 mmu set 000c0000, pos 000c0000 [17:27:03]1162 mmu set 000d0000, pos 000d0000 [17:27:03]1162 mmu set 000e0000, pos 000e0000 [17:27:03]1162 mmu set 000f0000, pos 000f0000 [17:27:03]1162 mmu set 00100000, pos 00100000 [17:27:03]1162 mmu set 00110000, pos 00110000 [17:27:03]ets Jun 8 2016 00:22:57 [17:27:03] [17:27:03]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:03]configsip: 0, SPIWP:0xee [17:27:03]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:03]mode:QIO, clock div:1 [17:27:03]load:0x3fff0018,len:4 [17:27:03]load:0x928b2121,len:-1725455839 [17:27:03]1162 mmu set 00010000, pos 00010000 [17:27:03]1162 mmu set 00020000, pos 00020000 [17:27:03]1162 mmu set 00030000, pos 00030000 [17:27:03]1162 mmu set 00040000, pos 00040000 [17:27:03]1162 mmu set 00050000, pos 00050000 [17:27:03]1162 mmu set 00060000, pos 00060000 [17:27:03]1162 mmu set 00070000, pos 00070000 [17:27:03]1162 mmu set 00080000, pos 00080000 [17:27:03]1162 mmu set 00090000, pos 00090000 [17:27:03]1162 mmu set 000a0000, pos 000a0000 [17:27:03]1162 mmu set 000b0000, pos 000b0000 [17:27:03]1162 mmu set 000c0000, pos 000c0000 [17:27:03]1162 mmu set 000d0000, pos 000d0000 [17:27:03]1162 mmu set 000e0000, pos 000e0000 [17:27:03]1162 mmu set 000f0000, pos 000f0000 [17:27:04]1162 mmu set 00100000, pos 00100000 [17:27:04]1162 mmu set 00110000, pos 00110000 [17:27:04]ets Jun 8 2016 00:22:57 [17:27:04] [17:27:04]rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) [17:27:04]configsip: 0, SPIWP:0xee [17:27:04]clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 [17:27:04]mode:QIO, clock div:1 [17:27:04]load:0x3fff0018,len:4 [17:27:04]load:0x928b2121,len:-1725455839 [17:27:04]1162 mmu set 00010000, pos 00010000 [17:27:04]1162 mmu set 00020000, pos 00020000 [17:27:04]1162 mmu set 00030000, pos 00030000 [17:27:04]1162 mmu set 00040000, pos 00040000 [17:27:04]1162 mmu set 00050000, pos 00050000 [17:27:04]1162 mmu set 00060000, pos 00060000 [17:27:04]1162 mmu set 00070000, pos 00070000 [17:27:04]1162 mmu set 00080000, pos 00080000 Serial port closed! `

[Jason2866]

Flashing manually you used mode DOUT and flash frequency 40 Mhz. The standard settings for Webcam build are flash mode QIO (faster) and flash frequency 80 Mhz (again faster). Your webcam does not statisfy the standards which a original AI-Thinker Webcam has. Or the power supply is not stable enough to power the webcam with the faster settings which draw more current

[codefaux]

To be clear, I just copy-pasted the command from the Tasmota documentation to flash the device, so it was less my idea, but point taken -- your app chooses settings which aren't compatible with some configurations, whereas the Tasmota documentation provides working defaults for most cases (even potentially unstable power supplies and/or devices which don't satisfy the 'standards' set by another device) thus providing a stable experience at the expense of a little speed.

I'll keep that in mind going forward and just do it manually, thanks a ton.

Just seemed odd, since the logs claimed to have done a data hash verification, seems like that might detect such a problem, lol. Sounds like they should patch the verification routine. Is there some way you can detect that issue and prevent the hard-infinite-loop from happening, at least? "If process X respawns more than ten thousand times in thirty seconds, something went wrong and maybe let's stop doing that" or something along those lines?

Also sorry for excessive pages of logcrap, I put it in the Code formatting but I didn't realize it was so long it was going to break that.

[Jason2866]

This log spam in first step can be a bad power supply. Most users are powering the device with the USB-serial adapter when flashing. With a good Usb serial adapter this is okay. But many ESP32 devices will bootloop when trying to start. You will see the garbage you had. In most cases the flashed device will work when powered correctly.

[Jason2866]

About flashing we (the Tasmota dev team) are working to port the ESP Webflasher to be used with Tasmota. So flashing needs only Chrome or Edge browser (and a USB serial adapter of course) to flash ALL Tasmota variants just with a click in Browser

[JustSpring]

Hi, I have the same problem. the esp32 is connected directly to the USB on the computer so I don't think it has a power problem. Do you have something I can do to fix it? Thanks

This log spam in first step can be a bad power supply. Most users are powering the device with the USB-serial adapter when flashing. With a good Usb serial adapter this is okay. But many ESP32 devices will bootloop when trying to start. You will see the garbage you had. In most cases the flashed device will work when powered correctly.

[Jason2866]

First working version of Tasmota Webflasher. The flashing functions are final. Only the different Firmware variants are missing. I added Tasmota32-webcam already. You can test if you want. It is here https://jason2866.github.io/Tasmota/

[Jason2866]

Issue is probably generated by this https://github.com/arendst/Tasmota/pull/12613 It is not a ESP_Flasher issue. It does what is told in the firmware files.

[clementcaen]

Thanks a lot @Jason2866, I have the same problem and I don't know why but I trying with the web solution and it works ! Since two days I try different solution, I install ubuntu, debian, try manually, ... and finally achieve with this simple click... 😅

[Jason2866]

We are heavily working on this tool. At the moment the webcam build is "out". I will add it again tomorrow. It is in early alpha state. We will announce when it is ready for daily use. There is some work to do...

[Jason2866]

Closing since no feedback using modified Tasmota webcam build (dout now default).