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Jegeva / ads2svd

turns cores form arm develloper studio to cmsis svds
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CMSIS-SVD SVD Consistency Checker isn't happy #6

Open jwinarske opened 4 years ago

jwinarske commented 4 years ago 
joel@hammer:~/git/CMSIS_5/CMSIS/Utilities/Linux64$ ./SVDConv ./Cortex-A72_AArch64.svd --generate=sfr

CMSIS-SVD SVD Consistency Checker / Header File Generator V3.3.35
Copyright (C) 2010 - 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.

Arguments: "./Cortex-A72_AArch64.svd" --generate=sfr 

*** ERROR M201: ./Cortex-A72_AArch64.svd (Line 11) 
  Tag <series> unknown or not allowed on this level.

*** ERROR M370: ./Cortex-A72_AArch64.svd (Line 24) 
  Register 'CPSR': <offset> not set.

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 24) 
  Ignoring Register : 'CPSR' (see previous message)

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 28) 
  Ignoring Fields  (see previous message)

*** ERROR M370: ./Cortex-A72_AArch64.svd (Line 30) 
  Register 'X0': <offset> not set.

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 30) 
  Ignoring Register : 'X0' (see previous message)

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 34) 
  Ignoring Fields  (see previous message)

*** ERROR M370: ./Cortex-A72_AArch64.svd (Line 36) 
  Register 'X1': <offset> not set.

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 36) 
  Ignoring Register : 'X1' (see previous message)

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 40) 
  Ignoring Fields  (see previous message)

*** ERROR M370: ./Cortex-A72_AArch64.svd (Line 42) 
  Register 'X2': <offset> not set.

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 42) 
  Ignoring Register : 'X2' (see previous message)

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 46) 
  Ignoring Fields  (see previous message)

*** ERROR M370: ./Cortex-A72_AArch64.svd (Line 48) 
  Register 'X3': <offset> not set.

*** INFO M211: ./Cortex-A72_AArch64.svd (Line 48)
Jegeva commented 4 years ago

yes, this is normal, these are core registers and don't have an offset since they are not memory projected. this is pending the discussing in the CMSIS issue.