[QUESTION] Exclude <= Ligature for VHDL Signal Assignment

[Nabav]

Question: How can I disable the ligature for <= combination?

In VHDL, it is used for both signal assignment and less than or equal.

Thanks.

[philippnurullin]

Unfortunately, from the font side it can't be done.

You can install the NL version of the font. It doesn't have ligatures. https://github.com/JetBrains/JetBrainsMono/tree/master/fonts/ttf