Closed whoozle closed 7 years ago
I think this is basically working 'as designed' since the 4XNN
, 5XNN
opcodes just increment the PC by 2 and i := long NNNN
is 4-bytes.
Correct. It didn't seem wise to modify the semantics of existing opcodes to accommodate new (XO-Chip specific) instructions, even if it might be more convenient in some cases.
those instructions are called SKIP, and semantically it's a conditional predicate. Since long form of assignment was added in XO chip, I'd expect it to skip it properly.
It didn't seem wise to modify the semantics of existing opcodes
Was adding 0 height mode for sprite instruction such modification too? :)
It does not seem rational to me, since the only old code it could possibly break — someone deliberately put always true in skip condition and skip f0 00 invalid opcode in some old code just for fun. I doubt it has been used anywhere.
I think this is basically working 'as designed' since the 4XNN, 5XNN opcodes just increment the PC by 2 and i := long NNNN is 4-bytes.
no instruction can possibly get PC value, so it does not matter if it skips 2 or 4 bytes, you can't get any side effect of it in chip8 execution environment
Lack of consistency here leads to hard-to-catch errors, if addr is also valid instruction. :(
Could you add error message in compiler then?
added error message for this https://github.com/JohnEarnest/Octo/pull/69
After sleeping on this, I've changed my mind. I will modify the interpreter to make all six conditional skip instructions skip over a double-wide i := long NNNN
. I can't think of any existing, valid programs it will break, and it makes the feature easier to use.
Thanks for bringing consistency here!
Consider the following example: