JosueOrtiz-fpga / zynq7000_eth_base_examples

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Build and Test packet redirection example #2

Open JosueOrtiz-fpga opened 3 months ago

JosueOrtiz-fpga commented 2 months ago

Look into Vitis SDT

JosueOrtiz-fpga commented 2 months ago

Resolved build errors by providing valid BASE_ADDR arguments to CFG functions which were previously being passed ID MACROs that are deprecated with the new SDT feature of Vitis 2024.

Project builds and application runs reporting all passing but visually inspecting the PL Rx Buffer contents shows that it is empty!

Current thoughts on next steps:

  1. Using an JTAG-AXI core, the BRAM contents can be read independently to see if RxBuffer gets filled or not which can isolate the issue.
  2. Evaluate ScuGicSelfTestExample and ScuGicInterruptSetup procedures in testperiph.c to ensure those are not producing false positives
JosueOrtiz-fpga commented 2 months ago

Thoughts after reading the Reference Manual GEM and GIC sections: