Open JosueOrtiz-fpga opened 3 months ago
Resolved build errors by providing valid BASE_ADDR arguments to CFG functions which were previously being passed ID MACROs that are deprecated with the new SDT feature of Vitis 2024.
Project builds and application runs reporting all passing but visually inspecting the PL Rx Buffer contents shows that it is empty!
Current thoughts on next steps:
Thoughts after reading the Reference Manual GEM and GIC sections:
Look into Vitis SDT