Halting, testbench, debug logic and fixes to the regfile and sign-extension - Githubissues

Jpnock / mips-verilog-cpu

A MIPS-I CPU implemented in SystemVerilog

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Halting, testbench, debug logic and fixes to the regfile and sign-extension #23

Closed dharmilshah99 closed 2 years ago

dharmilshah99 commented 2 years ago

Changes Made

Add skeleton files to test CPU - mips_cpu_bus_tb.v and cpu_ram.v

Jpnock commented 2 years ago

https://github.com/Jpnock/verilog-cpu/issues/24