control: Add byte-enables for LWL and LWR; make JAL and JALR unconditionally link

Jpnock / mips-verilog-cpu

A MIPS-I CPU implemented in SystemVerilog

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Closed Jpnock closed 2 years ago

Jpnock commented 2 years ago

[x] Closes #41
[x] Fixes the byte enables for LWL and LWR instructions
[x] Makes JAL and JALR instructions unconditionally write their link address (we do this anyway in the code somewhere else but this is a good failsafe)