test: Check that all registers are zero after reset - Githubissues

Jpnock / mips-verilog-cpu

A MIPS-I CPU implemented in SystemVerilog

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test: Check that all registers are zero after reset #57

Closed Jpnock closed 2 years ago

Jpnock commented 2 years ago

What does this PR do?

Adds tests to,

[x] Check that all registers are zero after a reset