JuliaComputing / xtrx_julia

XTRX LiteX/LitePCIe based design for Julia Computing
BSD 2-Clause "Simplified" License
1 stars 0 forks source link

SoapySDR driver: support for multiple devices #40

Closed maleadt closed 2 years ago

maleadt commented 2 years ago

With this, the XTRX device is per-path, and should discover automatically:

$ SoapySDRUtil --find
######################################################
##     Soapy SDR -- the SDR abstraction library     ##
######################################################

Found device 0
  driver = XTRX
  path = /dev/litepcie0

For serial-based identification, I had a look at the FPGA's DNA, but the returned value seems fishy:

diff --git a/fairwaves_xtrx.py b/fairwaves_xtrx.py
index 06c908a..a7efec7 100755
--- a/fairwaves_xtrx.py
+++ b/fairwaves_xtrx.py
@@ -27,6 +27,7 @@ from litex.soc.cores.gpio import GPIOOut
 from litex.soc.cores.spi_flash import S7SPIFlash
 from litex.soc.cores.bitbang import I2CMaster
 from litex.soc.cores.xadc import XADC
+from litex.soc.cores.dna  import DNA

 from litepcie.phy.s7pciephy import S7PCIEPHY

@@ -134,6 +135,10 @@ class BaseSoC(SoCCore):
         # XADC -------------------------------------------------------------------------------------
         self.submodules.xadc = XADC()

+        # DNA --------------------------------------------------------------------------------------
+        self.submodules.dna = DNA()
+        self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
+
         # PCIe -------------------------------------------------------------------------------------
         self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request(f"pcie_x2"),
             data_width = 64,
$ ./litepcie_util info
FPGA identification: LiteX SoC on Fairwaves XTRX 2022-08-29 12:25:45
FPGA dna: 0x01c01c1c1df01f1f
FPGA temperature: 58.3 °C
FPGA vccint: 0.95 V
FPGA vccaux: 1.77 V
FPGA vccbram: 0.95 V

Also, the internet tells me we should use the 64-bit FUSE_DNA instead of the 57-bit DNA_PORT, but I don't know how to read that from Verilog (i.e., just changing DNA_PORT to FUSE_DNA in LiteX' generators doesn't work).

Filed an issue for this, https://github.com/enjoy-digital/litex/issues/1411, but it's not critical.

sjkelly commented 2 years ago

FWIW these are the DNA numbers on two rev5:

0x0003fe00e00e00e0
0x0001f87819861801 

So there may not be an issue. Some devices just look suspect. I think we should go ahead with the gateware changes and ID reporting. I will push them here.

sjkelly commented 2 years ago

xref for DNA enable: bb901007f0a260b056a75205fc35082ee91c6d35