enjoy-digital
commented
2 years ago The issue is probably in the 32-bit to 64-bit Converter of the RX Datapath between the LimeLight interface and the DMA. With the tests I was doing, the issue was not seen since 32-bit data were still in order, but here you need 64-bit data to be in order for I1/Q1/I2/Q2.
The following changes should align the 32-bit to 64-bit converter to the frame signal and should fix the issue: https://github.com/enjoy-digital/xtrx_julia/commit/c964337453242490166277713867c4ecb0078b64
When performing digital loopback, TBB loopback, etc... we seem to randomly switch which rx channel is receiving. It's unclear whether this is due to a problem in transmission (e.g. we intend to transmit to TX1, but we transmit to TX2), in loopback configuration (we intend to loop TX1 -> RX1, but we instead loop TX1 -> RX2) or reception (we intend to read RX1, RX2, but instead we read RX2, RX1).
Performing register dumps mid-reception shows identical registers between the two cases, so I suspect some issue in the gateware, perhaps in the limelight interface code, since even the digital loopback suffers from this. Alternatively, we could potentially be facing some kind of DMA problem, since the data format is interleaved samples, if we slip by one full
Complex{Int16}, that would cause this issue.Reproducing this issue is straightforward, simply call
acquire_iq.jlwith the--digital-loopbackoption, and watch how some times the received signal is on RX1, and sometimes it's on RX2. If we need to create a smaller, more self-contained reproducer, I can help with that once the deadline this week is past.Examples of what this looks like: