maleadt
commented
2 years ago - [x] Expose necessary settings
- [x] Port Python calibration code
- [x] Verify clock delays in acquire_iq.jl
Closed maleadt closed 2 years ago
maleadt
commented
2 years ago maleadt
commented
2 years ago To run the Python calibration code:
Needs to be done in a directory with csr.csv, and can work over PCIe or over JTAG:
$ litex_server --jtag
# or
$ litex_server --pcie --pcie-bar=XX:00.0XX taken from lspci
If using litex_server over JTAG, use:
diff --git a/litex/tools/litex_client.py b/litex/tools/litex_client.py
index 2ae706e3..9daa1bc5 100644
--- a/litex/tools/litex_client.py
+++ b/litex/tools/litex_client.py
@@ -120,8 +120,8 @@ def dump_registers(csr_csv, port, filter=None):
bus.open()
# On PCIe designs, CSR is remapped to 0 to limit BAR0 size.
- if hasattr(bus.bases, "pcie_phy"):
- bus.base_address = -bus.mems.csr.base
+ # if hasattr(bus.bases, "pcie_phy"):
+ # bus.base_address = -bus.mems.csr.base
for name, register in bus.regs.__dict__.items():
if (filter is None) or filter in name:Then --regs should` work (note that it dumps sane reg values, not 0xfffffffff for LMS regs):
$ litex_cli --regs
0xf0000000 : 0x0b00006f uart_rxtx
0xf0000004 : 0x00000013 uart_txfull
0xf0000008 : 0x00000013 uart_rxempty
0xf000000c : 0x00000013 uart_ev_status
...Easiest is by disabling most of the XTRXDevice destructor so that the device (both the FPGA and the LMS) is left in a configured state after running, e.g., acquire_iq.jl --digital-loopback. The digital loopback needs to be enabled.
Also needs csr.csv:
$ python test_lms7002m_digital_interface.py --tx-rx-scan
TX-RX Delay Scan...
TX / RX 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
00 | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
01 | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
02 | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
...Instead of the previous post, you can now just use the Julia port in combination with the SoapySDR driver:
$ jl --project calibrate_delays.jl [settings]
[INFO] SoapyXTRX initializing...
[INFO] LMS7002M info: revision 1, version 7
[INFO] CGEN tune 122.880000 MHz (fref=26.000000 MHz) begin
[INFO] SoapyXTRX initialization complete
[INFO] SXX tune 1575.000000 MHz (fref=26.000000 MHz) begin
[WARNING] SoapyXTRX::setSampleRate(): not a power of two factor: TSP Rate = 30.720000 MHZ, Requested rate = 6.000000 MHz
[INFO] SXX tune 1575.000000 MHz (fref=26.000000 MHz) begin
[WARNING] SoapyXTRX::setSampleRate(): not a power of two factor: TSP Rate = 30.720000 MHZ, Requested rate = 6.000000 MHz
[INFO] SXX tune 1575.000000 MHz (fref=26.000000 MHz) begin
[WARNING] SoapyXTRX::setSampleRate(): not a power of two factor: TSP Rate = 122.879999 MHZ, Requested rate = 6.000000 MHz
[INFO] SXX tune 1575.000000 MHz (fref=26.000000 MHz) begin
[WARNING] SoapyXTRX::setSampleRate(): not a power of two factor: TSP Rate = 122.879999 MHZ, Requested rate = 6.000000 MHz
TX / RX 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
00 | - X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
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[INFO] Power down and cleanupAnd for manual control:
SoapySDR.SoapySDRDevice_writeSetting(dev, "FPGA_RX_DELAY", "16")
SoapySDR.SoapySDRDevice_writeSetting(dev, "FPGA_TX_DELAY", "16")This looks good to go, and a definite improvement, but it doesn't fix the signal spikes from https://github.com/JuliaComputing/xtrx_julia/issues/41. Here I've ran the current acquire_iq.jl test script using the TBB loopback for all values of RX/TX clock delay: http://sagittarius.maleadt.net/public/delay/
I don't see many differences, except for very low delay values (which were already detected as bad by the calibration scripts; see previous post) all plots have zero-crossing spikes and signal bleed.
maleadt
commented
2 years ago Ah, turns out I didn't only need to set CGEN to 400MHz, but also increase the sample rate to, say, 40MHz. Doing so I can replicate the bad signal (this is with the digital loopback):
For these parameters the calibration plot is interesting:
TX / RX 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
00 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
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08 | ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✗
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24 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
25 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
26 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
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28 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
29 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
30 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗
31 | ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗Picking a combination more near the middle of the window, say 12/12, yields better plots, but only for the real part:
