DAC tuning of VCTCXO for reference clock

[staticfloat]

We need to tune the reference clock (both on the XTRX, for single-board operation, and on the XYNC board) to get as close to our stated reference frequency (26MHz for single-board operation) as possible. We have the ability to count reference clock cycles on the RISC-V core, but I'm not 100% certain where the clock that drives the RISC-V core comes from, and so I don't know quite how accurate the cycle count is for reference clock tuning.

Beyond the signal source, we also need to have a coherent story for tuning both the XTRX and the XYNC, so we need a way to tell the RISC-V core on the first XTRX to tune the other DAC for the other VCTCXO.

Possible ways forward:

• Continue to use the base RISC-V clock for cycle counting, plumb through an RPC call that allows for DAC tuning from the Julia userspace. We would need to surface the reference clock and verify that the tuning results are actually good before choosing this.
• Integrate PPS signal reception, hook it up to an interrupt on the RISC-V core, use that for precise second-long tuning values.

One of the things that I don't like about the PPS signal idea is that I'd like to calibrate fast; if we want full precision, we essentially will need to do a binary walk over the parameter space (should take ~12 steps to find the optimal value, as it's a 12-bit value) and so if we only get a (single, high-precision) measurement once every 12 seconds, that's a little slow in my book. I'd much rather be able to, for instance, take 1ms measurements very quickly for the first few bits, then increase to 10ms measurements, and finally 100ms measurements for the last few steps, so that we can finish the whole thing in like less than 0.5 seconds.

Concrete TODOs

• [ ] Decide on calibration timing signal source
• [ ] Build method to begin DAC tuning from Julia userspace
• [ ] Build ability for RISC-V core to control XYNC VCTCXO tuning DAC.

[staticfloat]

For reference, The XTRX has a clock estimation block that looks like this: https://github.com/xtrx-sdr/fpga-source/blob/bd64676fc6a1989c14fa2892b09b12f204e4cd4a/lib/xtrx/clk_estimator.v

[sjkelly]

An update on this one: The XYNC carrier has a pre-calibrated precision VCTCXO on it that is stable to +/- 50ppb. This is more than sufficient for our needs. Further trimming is possible, but we will disregard for now: http://www.conwin.com/datasheets/tx/tx395.pdf