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JuliaComputing / xtrx_julia

XTRX LiteX/LitePCIe based design for Julia Computing
BSD 2-Clause "Simplified" License
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rxtools testing #98

Closed staticfloat closed 2 years ago

staticfloat commented 2 years ago

These changes allow me to receive some nice signals on the XTRX while using rx_sdr.

I ran:

./build/bin/rx_sdr -F CS16 -c 0,1 -f 600000000 -n 4000000 /tmp/test.iq

Followed by:

julia -i --project plot_iq_file.jl /tmp/test.iq.rx0

And then finally:

julia>  plot_cisoid(data, plot_file)

Which gave me:

test iq rx0

I intend to use the cisoid fit to automatically detect buffer underruns. Anecdotally, I have seen rx_sdr give me a discontinuity, but it seems to be much, much rarer than when we receive from Julia. Of course, I'm only receiving ~2 seconds of data here, we'll want to receive much more than this when debugging.

sjkelly commented 2 years ago

There are some issues now with acquire_iq.jl I am tracking down. ~The sign extension will also break the test pattern scripts~. Regardless for performance, we will want the sign extension on the FPGA, so I think it would be good to update the pattern checks here as well.

staticfloat commented 2 years ago

Yeah, I don't actually think the sign extension being done in C code is the right thing here. I think really what we should be doing is transmitting 3-byte CS12 clusters, not transmitting CS16 at all. But because I got frustrated by the values always being wrong at different points through the stack, I decided to fix them here (for now)

sjkelly commented 2 years ago

The acquire_iq issues I was seeing were cleared up after a reboot. I am not sure what was going on. test_pattern is also good. This looks like a good simplification.