Closed jlchan closed 2 years ago
I can reproduce:
julia> StructArrays.foreachfield((out,x) -> matmul!(out, A, x), out, x)
signal (7): Bus error
in expression starting at REPL[5]:1
macro expansion at /home/chriselrod/.julia/dev/VectorizationBase/src/llvm_intrin/vbroadcast.jl:74 [inlined]
_vbroadcast at /home/chriselrod/.julia/dev/VectorizationBase/src/llvm_intrin/vbroadcast.jl:80 [inlined]
vbroadcast at /home/chriselrod/.julia/dev/VectorizationBase/src/llvm_intrin/vbroadcast.jl:96 [inlined]
macro expansion at /home/chriselrod/.julia/dev/LoopVectorization/src/reconstruct_loopset.jl:713 [inlined]
_turbo_! at /home/chriselrod/.julia/dev/LoopVectorization/src/reconstruct_loopset.jl:713 [inlined]
ploopmul! at /home/chriselrod/.julia/dev/Octavian/src/macrokernels.jl:30 [inlined]
packaloopmul! at /home/chriselrod/.julia/dev/Octavian/src/macrokernels.jl:138
unknown function (ip: 0xbfdfa82222d17b41)
Allocations: 75050282 (Pool: 74990981; Big: 59301); GC: 46
fish: Job 1, '/home/chriselrod/Documents/lang…' terminated by signal SIGBUS (Misaligned address error)
I can reproduce on skylake-avx512, but not on tigerlake. Both have AVX512. LoopVectorization should be treating them identically here, Octavian nearly so (cache sizes differ).
FWIW, I was able to reproduce my initial error on Xeon Gold 6138 (Skylake), 6230 (Cascade Lake), and 6248 (also Cascade Lake).
@sloede noticed this error when running Trixi.jl on a Xeon Gold processor
MWE:
The output is
The MWE was run with
julia --threads=1 mwe.jl
on an Intel(R) Xeon(R) Gold 6248 CPU @ 2.50GHz with[6fd5a793] + Octavian v0.3.8
,[90137ffa] + StaticArrays v1.2.13
, and[09ab397b] + StructArrays v0.6.3
.Unfortunately, it seems like we can only produce this error on the cluster; our personal laptops and Linux desktops don't seem to have an issue.