Support for "sharedextbus" and "errextbus"

Juniper / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Apache License 2.0

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Support for "sharedextbus" and "errextbus" #56

Closed kdloe closed 5 years ago

kdloe commented 5 years ago

The ORDT wiki documentation lists "sharedextbus" and "errextbus" as unsupported attributes. When can/will these become supported attributes? :-)

sdnellen commented 5 years ago

Not this week ;) ...or anytime soon realistically.

Currently tool only supports the following aggregations for creating external regions:

single regs/reg arrays w/ external tag
single regfiles/regfile arrays w/ external tag
child addrmaps (treated as an external regfile)
single regs/reg arrays within a replicated regfile hierarchy w/ external tag and rep_level option

It isn't clear what the errextbus actually does from the rdl1.0 spec, so it wasn't implemented. However, all generated external interfaces have a nack input by default for indicating an invalid transaction occurred - this indication is returned to the main decoder interface.

kdloe commented 5 years ago

Hello - We use the shared external bus to connect to multiple SRAMS that have been mapped into the register space and save on signals. We also use the errextbus for returning the SRAM secded errors.

sdnellen commented 5 years ago

Currently you will need to wrap elements in a single regfile to get a single external interface. Only exception is case of regs in replicated regfile hierarchy, which can be collapsed to single i/f using rep_level external option.

Can return nack from external region for ecc/parity fails / ack for valid transactions. Generally use interrupt scheme for fail detect/logging of ram fails.

kdloe commented 5 years ago

Tried this out and we think it will work for us.