sdnellen
commented
5 years ago ordt uses a general interface between decoder and logic submodules for all registers - it is assumed that synthesis will clean these up. It is key to not retain submodule hierarchy in synthesis as in addition to unused signals, there are a number of replicated common signals that will have non-optimum structure if sub-level ports are retained. Need to add a note to the docs re this behavior.
sjalloq
Hi, I'm testing out an interrupt register that is set by hardware and cleared by a software read. I noted that along with the _intr input from the HW, there is also a redundant write path from the software side generated.
In the following Verilog output, the inputs d2l_u_1_my_irq_0_w* to the root address map are unused.
regfile.v.txt
regfile.rdl.pp.final.txt