Juniper / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Apache License 2.0
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How to connect the APB bus to the generated verilog module? #73

Open zhajio1988 opened 5 years ago

zhajio1988 commented 5 years ago

hi, i want to use APB master to configure register. if i use ORDT to generate the register module, which processor interface do i should use? (Parallel processor interface, Leaf processor interface...) thanks a lot.

sdnellen commented 5 years ago

i'd use parallel - should get you very close to what is needed for apb.

zhajio1988 commented 5 years ago

@sdnellen thanks, but why don't implement a apb bus or ahb bus register file? Copyright problem?

sdnellen commented 5 years ago

just time - never needed apb specifically. if you provide tested convert logic from parallel to apb, can add it as an option