Open kongty opened 4 years ago
When there are two processor interfaces, decoder logic is out of sync when using parallel mode.
parallel
address and data signals are synced to one cycle earlier than write or `read signal, so it does not write to registers.
address
data
write
I will add an example soon.
When there are two processor interfaces, decoder logic is out of sync when using
parallelmode.addressanddatasignals are synced to one cycle earlier thanwriteor `read signal, so it does not write to registers.I will add an example soon.