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[TMAKE]: building nv_small in verif/testbench/trace_generator
/bin/mkdir -p ../../../outdir/nv_small/verif/testbench/trace_generator
/home/nvdla/synopsys/bin/vcs +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/spec/manual +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/ral +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/vip/csb_agent +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/env +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/scenarios +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/resources +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/tests/uvm_tests +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/coverage +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/verif/vip/mem_man +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/verif/vip/surface_generator +incdir+/home/nvdla/NVDLA/git-nvdla/nvdla/verif/vip/csb_agent -sverilog -ntb_opts uvm-1.2 -timescale=1ns/1ns -assert enable_diag -line -full64 +v2k +libext+.vlib+.v+.sv+.svh +warn=noTFIPC +warn=noTMR /home/tools/debussy/verdi3_2016.06-SP2-9/share/PLI/VCS/LINUX64/pli.a +vcsd -P /home/tools/debussy/verdi3_2016.06-SP2-9/share/PLI/VCS/LINUX64/novas.tab /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/spec/defs/project.vh /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/env/fp_func_dpi.cpp /home/nvdla/NVDLA/git-nvdla/nvdla/verif/vip/mem_man/mem_man_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/verif/vip/surface_generator/surface_generator_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/spec/manual/ordt_uvm_reg_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/ral/nvdla_ral_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/vip/csb_agent/csb_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/coverage/nvdla_coverage_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/resources/nvdla_resource_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/scenarios/nvdla_scenario_pkg.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/env/nvdla_tg_common.svh /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/env/nvdla_tg_core.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/env/nvdla_tg_base_test.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/testbench/trace_generator/env/nvdla_tg_top.sv /home/nvdla/NVDLA/git-nvdla/nvdla/outdir/nv_small/verif/tests/uvm_tests/nvdla_test_suite.sv -l ../../../outdir/nv_small/verif/testbench/trace_generator/simv.build.log -o ../../../outdir/nv_small/verif/testbench/trace_generator/simv -Mdir=../../../outdir/nv_small/verif/testbench/trace_generatorcsrc
Chronologic VCS (TM)
Version L-2016.06_Full64 -- Mon Apr 23 17:57:34 2018
Copyright (c) 1991-2016 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Error-[COP_PLI_TAB] Cannot open pli table file
Cannot open pli table file
'/home/tools/debussy/verdi3_2016.06-SP2-9/share/PLI/VCS/LINUX64/novas.tab'.
Please make sure tab file exists and readable.
Bad command line arg encountered