Closed IveanEx closed 2 months ago
I formatted the code of these two using verible. That is why you may see soooo many line changes in this commits😂😂
Ok! It seems only minor changes and format things.
Ok, but I would refrain from autoformatting existing files. The goal of github is to see if we changed something. Could you please bring the non-auto formatted back then just add your changes?
Thanks!
Reverted 😊
This PR renames the log of cores and DMAs during the simulation to avoid the log being overridden by core at the same position of one chip, but at different chips.