Closed morainer closed 9 months ago
BTW, according to the calculating method mentioned in the paper, I think that the MAC operation inside of each PE should be 320 but not 1600, as the FYu 5 LOOP is a spatial reuse factor and it should not be considered. Please let me know where I got it wrong.
Hi,
The architecture generator as described in the original paper isn't directly available as a Stage but can be created to your liking by modifying the OperationalArray and MemoryHierarchy into a new Core and Accelerator. You can read more here and an example of modifying the architecture can be found here, where the PE array is scaled with a given factor.
Regarding the MAC count inside each PE, I believe you are correct. @LY-Mei can you confirm?
Very appreciate to receive your answers. I will wait for @LY-Mei ‘s confirmation. And, would you like to offer me an example to use the PEArrayScalingStage?
Yes, you are right. The MAC operation inside of each PE should be 320. Thanks for catching it!
I can not find any code or document that describe the details of the ARCHITECTURE GENERATOR. Could you offer an example for me? PS: The paper of zigzag is https://ieeexplore.ieee.org/document/9360462#:~:text=This%20article%20introduces%20ZigZag%2C%20a%20rapid%20DSE%20framework,uneven%20mapping%20opportunities%20and%20smart%20mapping%20search%20strategies.