Closed drichmond closed 8 years ago
What was the resolution of this issue?
Wasn't Xilinx specific. In the end, the state machine in tx_port_monitor had a bug in it, that was caused by an earlier fix on a related issue.
Why do you ask?
I am seeing an issue that sounds similar where sometimes the 1st two DWORDS are coming through wrong. It seems to be much less prevalent using the user_clk output of the RIFFA module vs my internal 100MHz asynchronous clock. Was the issue resolved in 2.2.2?
Yes
On Nov 18, 2016, at 11:11 AM, cjmraziii notifications@github.com wrote:
I am seeing an issue that sounds similar where sometimes the 1st two DWORDS are coming through wrong. It seems to be much less prevalent using the user_clk output of the RIFFA module vs my internal 100MHz asynchronous clock. Was the issue resolved in 2.2.2?
— You are receiving this because you modified the open/close state. Reply to this email directly, view it on GitHub https://github.com/KastnerRG/riffa/issues/13#issuecomment-261615673, or mute the thread https://github.com/notifications/unsubscribe-auth/AGFUdJKQGAnExhBbZtW78AyJLIc8Ogm7ks5q_fhlgaJpZM4JgRDp.
This causes a missing first-dword in about 1-in-10 transfers.
Does not seem to affect Altera (unlikely it's a logic bug in our code)