Open jixi2018 opened 5 years ago
I tried to simulate the riffa example without the PCIe core. I created a testbench to instantiate the following modules(I am using Xilinx KC705 board)
riffa_wrapper_kc705
// Parameters .C_LOG_NUM_TAGS (C_LOG_NUM_TAGS), .C_NUM_CHNL (C_NUM_CHNL), .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH), .C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES)) riffa....
chnl_tester #( .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH) ) dut ...
I initialize the inputs of the riffa_wrapper_kc705 as following:
wire [SIG_BUSID_W-1:0] cfg_bus_number = {SIG_BUSID_W{1'b0}}; wire [SIG_DEVID_W-1:0] cfg_device_number = {SIG_DEVID_W{1'b0}}; wire [SIG_FNID_W-1:0] cfg_function_number = {SIG_FNID_W{1'b0}}; wire [SIG_CFGREG_W-1:0] cfg_command = {SIG_CFGREG_W{1'b0}}; wire [SIG_CFGREG_W-1:0] cfg_dcommand = 16'h2810; wire [SIG_CFGREG_W-1:0] cfg_lstatus = 16'h1000; wire [SIG_CFGREG_W-1:0] cfg_lcommand = {SIG_CFGREG_W{1'b0}}; wire [SIG_FC_CPLD_W-1:0] fc_cpld = {SIG_FC_CPLD_W{1'b0}}; wire [SIG_FC_CPLH_W-1:0] fc_cplh = {SIG_FC_CPLH_W{1'b0}};
SIG_BUSID_W-1:0] cfg_bus_number = {
SIG_DEVID_W-1:0] cfg_device_number = {
SIG_FNID_W-1:0] cfg_function_number = {
SIG_CFGREG_W-1:0] cfg_command = {
SIG_CFGREG_W-1:0] cfg_dcommand = 16'h2810; wire [
SIG_CFGREG_W-1:0] cfg_lcommand = {
SIG_FC_CPLD_W-1:0] fc_cpld = {
SIG_FC_CPLH_W-1:0] fc_cplh = {
In my testbench, I drive the following signals to generate valid transaction:
M_AXIS_RX_TDATA M_AXIS_RX_TKEEP M_AXIS_RX_TLAST M_AXIS_RX_TVALID M_AXIS_RX_TUSER S_AXIS_TX_TREADY
I check the waveform, there was no activities on RXCHNL* signals of the riffa RX output side connecting the chnl_tester. Did anybody experience the similar issue?
I tried to simulate the riffa example without the PCIe core. I created a testbench to instantiate the following modules(I am using Xilinx KC705 board)
riffa_wrapper_kc705
(/AUTOINSTPARAM/
chnl_tester #( .C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH) ) dut ...
I initialize the inputs of the riffa_wrapper_kc705 as following:
wire [
SIG_BUSID_W-1:0] cfg_bus_number = {SIG_BUSID_W{1'b0}}; wire [SIG_DEVID_W-1:0] cfg_device_number = {SIG_DEVID_W{1'b0}}; wire [SIG_FNID_W-1:0] cfg_function_number = {SIG_FNID_W{1'b0}}; wire [SIG_CFGREG_W-1:0] cfg_command = {SIG_CFGREG_W{1'b0}}; wire [SIG_CFGREG_W-1:0] cfg_dcommand = 16'h2810; wire [SIG_CFGREG_W-1:0] cfg_lstatus = 16'h1000; wire [SIG_CFGREG_W-1:0] cfg_lcommand = {SIG_CFGREG_W{1'b0}}; wire [SIG_FC_CPLD_W-1:0] fc_cpld = {SIG_FC_CPLD_W{1'b0}}; wire [SIG_FC_CPLH_W-1:0] fc_cplh = {SIG_FC_CPLH_W{1'b0}};In my testbench, I drive the following signals to generate valid transaction:
M_AXIS_RX_TDATA M_AXIS_RX_TKEEP M_AXIS_RX_TLAST M_AXIS_RX_TVALID M_AXIS_RX_TUSER S_AXIS_TX_TREADY
I check the waveform, there was no activities on RXCHNL* signals of the riffa RX output side connecting the chnl_tester. Did anybody experience the similar issue?