Closed FrankChuKontex closed 4 months ago
We found the bug. It happen at tx_multiplexer_128.v Line 152 assign wWrData = WR_DATA[(wCountChnl C_PCI_DATA_WIDTH) +: C_PCI_DATA_WIDTH]; After Vivado 2018 and 2023 synthesis(we have got), the wCountChnl only got 1 bit. We change to that line to : wire[11:0] sel = wCountChnl C_PCI_DATA_WIDTH; assign wWrData = WR_DATA[sel +: C_PCI_DATA_WIDTH]; Everything go well. The tx_multiplexer_64.v and tx_multiplexer_32.v might has the same issue.
Greeting, I try the sample code in AC701. (I use vivado 2018.3) After change the C_NUM_CHNL = 3 The channel 3 recived data become all 0 Any idea ?