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KenDickey / BeeYourself

Experiments in porting Powerlang/Bee-DMR to Cuis
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Risc-V and Risc5 are not the same cpu #1

Open Kirtai opened 3 years ago

Kirtai commented 3 years ago

Just a quick note to mention that Risc5 is a CPU developed by Niklaus Wirth for Project Oberon. It's not the same as the Risc-V CPU architecture.

Not that it's likely to confuse people other than unusual hardware nerds like myself but it would be nice to use Risc-V in all places. :)

KenDickey commented 3 years ago

On 2021-05-09 03:08, Kirtai wrote:

Just a quick note to mention that Risc5 is a CPU developed by Niklaus Wirth for Project Oberon. It's not the same as the Risc-V CPU architecture.

Not that it's likely to confuse people other than unusual hardware nerds like myself but it would be nice to use Risc-V in all places. :)

I find "5" shorter to spell and less confusing than "-V".

Also, no Mayan numerals on my keyboard! ;^)

Note that the PowerLang and RISCy code is waaaaaayyy pre-alpha!

Just getting the bits together. Check back next year sometime..

Cheers, -KenD

Kirtai commented 3 years ago

No worries, I just thought I'd mention it since it did confuse me on first sight. But then again, I am one of those people who are fascinated by unusual and obscure hardware. :)

KenDickey commented 1 year ago

updates..