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KenWillmott / HD6303EVB

Hitachi HD63C03YP Evaluation Board
MIT License
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MR (memory ready) with slow I/O #4

Open KenWillmott opened 1 year ago

KenWillmott commented 1 year ago

MR signal extends E signal time. It can be tapped from the 02 output of U6B decoder, then all memory accesses from C000-D000 in the bus address range will be slower. Some legacy parts are not fast enough for 2MHz bus speeds so it should be an on board jumper option.

KenWillmott commented 1 year ago

It's fully tested now. With the 3.0MHz CPU clock, the peripheral E clock stretch produces an effective bus access speed of 1.0MHz for peripherals (automatic mode produces 1/3 speed). Only doubts are how to implement it as a feature.