We desperately need continuous integration/deployment for this processor design. One of the steps to getting there will be to fix the following issues:
[ ] mimpid value in Verilog is hardwired; somehow it needs to receive new field values by the time the master branch is updated by the CI system. That way, the master branch always has the most up-to-date version of a synthesizable processor.
[ ] mimpid fields in the Markdown documentation is hardwired; somehow, these also need to be updated by the time the master branch is updated. This ensures the documentation matches silicon.
We desperately need continuous integration/deployment for this processor design. One of the steps to getting there will be to fix the following issues: