Fix Verilog so unconnected pins are explicit.

[sam-falvo]

• [x] fence_o
• [x] trap_o
• [x] cause_o
• [x] mepc_o
• [x] mpie_o
• [x] mie_o
• [x] ddat_o
• [x] dadr_o
• [x] dwe_o
• [x] dcyc_o
• [x] dstb_o
• [x] dsiz_o
• [x] dsigned_o