I made this footprint for TLC5947, but I'm hoping it can be a general footprint for any HTSSOP-32 chip.
I started with the existing TSSOP-32_6.1x11mm_Pitch0.65mm footprint, and just added the thermal pad, so everything except the thermal pad is identical to that footprint. Note that there is a slight discrepancy, because the TLC5947 datasheet (on page 23) gives the package dimensions as 6.2 x 11.1, while the existing TSSOP-32 footprint is for 6.1 x 11. But, I figure what's 0.1mm among friends?
I created the thermal pad as specified on page 25 of the TLC5947 datasheet. I used several pads to create the thermal pad structure:
A big 5.2 x 11 SMT pad only on the copper layers, to create the copper pad shown in the figure.
A smaller 4.11 x 4.36 SMT pad for the mask and paste, to create what the datasheet calls the "Solder Mask Defined Pad." The datasheet gives different dimensions for this area, depending on the stencil thickness, which isn't really possible to do in a general-purpose library.
A 4x8 array of THT pads, to create the thermal vias.
I think this arrangement creates what the datasheet asks for. However, this weird use of layers makes check_kicad_mod.py very unhappy. It says I am violating rules 8.3 and 9.4.
There was some discussion of thermal pads on the forum.
I made this footprint for TLC5947, but I'm hoping it can be a general footprint for any HTSSOP-32 chip.
I started with the existing
TSSOP-32_6.1x11mm_Pitch0.65mm
footprint, and just added the thermal pad, so everything except the thermal pad is identical to that footprint. Note that there is a slight discrepancy, because the TLC5947 datasheet (on page 23) gives the package dimensions as 6.2 x 11.1, while the existing TSSOP-32 footprint is for 6.1 x 11. But, I figure what's 0.1mm among friends?I created the thermal pad as specified on page 25 of the TLC5947 datasheet. I used several pads to create the thermal pad structure:
A big 5.2 x 11 SMT pad only on the copper layers, to create the copper pad shown in the figure.
A smaller 4.11 x 4.36 SMT pad for the mask and paste, to create what the datasheet calls the "Solder Mask Defined Pad." The datasheet gives different dimensions for this area, depending on the stencil thickness, which isn't really possible to do in a general-purpose library.
A 4x8 array of THT pads, to create the thermal vias.
I think this arrangement creates what the datasheet asks for. However, this weird use of layers makes
check_kicad_mod.py
very unhappy. It says I am violating rules 8.3 and 9.4.There was some discussion of thermal pads on the forum.