MIPS break instruction discrepancy

[queueRAM]

I'm seeing a discrepancy between the way armips and gas encode the break instruction. The way I read the instruction set (least significant 6-bits=0xD, most significant 6-bits=0, middle 20-bits=immediate 'code'), armips seems correct, but both binutils and llvm do it another way. Can anyone shed some light on this?

armips:

$ echo '.n64 :: .create "break.bin", 0 :: break 7 :: .close' > break.s
$ armips break.s
$ mips64-elf-objdump -b binary -EB -mmips -D break.bin
Disassembly of section .data:

00000000 <.data>:
   0:   000001cd        break   0x0,0x7

# not just binutils!:
$ rasm2 -a mips -D -e -Bf break.bin
0x00000000   4                 000001cd  break 0, 7

gas:

$ echo "break 7" | mips64-elf-as -o break.o -
$ mips64-elf-objdump -d break.o
Disassembly of section .text:

00000000 <.text>:
   0:   0007000d        break   0x7

[unknownbrackets]

https://github.com/gittup/binutils/blob/gittup/opcodes/mips-opc.c#L330

I guess it's a different interpretation of the one arg vs two arg syntax? Seems influenced by the encoding for tge, etc.

-[Unknown]