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Kingcom / armips

An assembler for various ARM and MIPS platforms. Builds available at http://buildbot.orphis.net/armips/
MIT License
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Is blh as a sole instruction supported? / Any plans to add it if not? #64

Closed charleysdrpepper closed 8 years ago

charleysdrpepper commented 8 years ago

I know that the list of instructions at https://github.com/Kingcom/armips/blob/master/Archs/ARM/ThumbOpcodes.cpp shows:

{ "bl",     "/#I\x16",          0xF800, THUMB_TYPE19,   4,  THUMB_IMMEDIATE|THUMB_BRANCH|THUMB_LONG },

However seeing as it says bl instead of blh ... and that the mask still has x16 in it, I figured maybe it went with the original bl instruction.

The reason why I ask, is, I know that games can use blh as a sole instruction as seen by Golden Sun 1/2 's code... Where they manually put a RAM address into LR, and do blh 0x0000 to call it. (The map code stuff...)

We know that in a normal bl instruction, It's basically: 1st instruction = LR = PC+4+(nn SHL 12) 2nd instruction = PC = LR + (nn SHL 1), and LR = PC+2 OR 1 ...just to point out that blh (0xF800) works the same way regardless of whether it has its counterpart or not.

I know that there are alternatives that I could do like using other instructions, or even doing .halfword 0xF800 for worst case scenario.

Edit again: Gbatek seems to refer to it as "BL LR+imm" ... -

Kingcom commented 8 years ago

Interesting. I wasn't aware this was allowed. I'll add support for it.

Kingcom commented 8 years ago

Okay, I added both ways to write the opcode. Let me know if there are any further issues.