VHDL support for testing modules

[CHV123]

I've got an old version of koheron-sdk that I'm using and was thinking about updating, I've added vhdl support to the test_module.tcl script (copying the support added to the test_cores.tcl) and it might be useful for others.

output of "git diff fpga/vivado/test_module.tcl":

index 3de2158..17f7547 100644
--- a/fpga/vivado/test_module.tcl
+++ b/fpga/vivado/test_module.tcl
@@ -14,7 +14,7 @@ file delete -force \
   $output_path/$project_name.xpr \
   $output_path/$project_name.sim

-create_project -part $part $project_name $output_path
+create_project -force -part $part $project_name $output_path

 set_property IP_REPO_PATHS $output_path/../cores [current_project]
 update_ip_catalog -rebuild -scan_changes
@@ -34,7 +34,7 @@ make_wrapper -files [get_files $bd_path/system.bd] -top

 add_files -norecurse $bd_path/hdl/system_wrapper.v

-add_files -norecurse $project_path/test_bench.v
+add_files -norecurse [glob -nocomplain $project_path/test_bench.v*] -fileset sim_1

 set_property -name {xsim.simulate.runtime} -value {100000ns} -objects [current_fileset -simset]

[jeanminet]

thanks !