tvanderbruggen
commented
4 months ago Hi,
The clock going from the FPGA to the clock generator is (see DRC):
set_property PACKAGE_PIN U15 [get_ports clk_gen_out_n] ;# SRCC
set_property PACKAGE_PIN U14 [get_ports clk_gen_out_p] ;# SRCCThe USER_IOx are connected to the GPIO expander (just like the ALPHA250) and are 3.3V logic level.
The other IOs on the expansion connector are directly connected to the FPGA bank 35 supplied with 1.8 V
(because this bank also interface an ADC).
You must make sure the FPGA is turned on before applying any voltage on these pins, the VCCIO_1V8
(pin 54 of the connector) should be use for power sequencing.
From the FPGA you can drive the SPI buses to the full speed of the precision DAC (50 MHz) and ADC (10 MHz).
The precision DAC has been used for control loops up to 244 ksps (see https://arxiv.org/pdf/2311.00216). There is no filter at the DAC output.
The maximum sampling rate of the ADC is 19.2 ksps (Nyquist frequency 9.6 kHz). There is a 7.96 kHz anti-aliasing filter at the input of each channel. At full SPI bus speed you can read about 200 ksps, so ADC conversion time is limiting.
hi
i was which pin on fpga is being used to connect to the input of the clock tree if we wanted to use clock from fpga as ref clock. also can you please confirm the the voltage on the GPIO pins; from what I understand, only USER_IOx on alpha250-4 is connected to a level shifter?
additionally, have you tried driving the precision DACs / ADC from the FPGA; I would like to know what kind of sample rate is realistic on these devices i.e. what kind of rate can I poll the data from the FPGA (not the PS) using the spi bus.