Control Unit (Instruction Decoder) design & test

[Kooscii]

lw : out STD_LOGIC;
sw : out STD_LOGIC;
branch : out STD_LOGIC;
bnc_type : out STD_LOGIC_VECTOR (1 downto 0);
jump : out STD_LOGIC;
funct : out STD_LOGIC_VECTOR (2 downto 0);
op2src : out STD_LOGIC;
regdst : out STD_LOGIC;
regwrt : out STD_LOGIC;
inst : in STD_LOGIC_VECTOR (31 downto 0));

• Asynchronous

• lw: HIGH when instruction is LW

• sw: HIGH when instruction is SW

• branch: HIGH when instruction is BLT | BEQ | BNE

• bnc_type: 01 when BNE; 11 when BEQ; 10 when BLT

• jump: HIGH when instruction is JMP

• funct: to be disscussed

• op2src: HIGH when instruction is I-type (except BXX)

• regdst: HIGH when instruction is R-type

• regwrt: HIGH when opcode == 00 to 07

Progress

• [ ] Functional simulation passed.
• [ ] Timing simulation passed.