Data memory design & test

[Kooscii]

rd : out STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (31 downto 0);
wd : in STD_LOGIC_VECTOR (31 downto 0));

• Design a big-endian byte-addressing memory block.
• Reading data is asynchronous, rd = MEM[addr:addr+4].
• Writing data is synchronous, MEM[addr:addr+4] = wd when rising_edge(clk) and we is HIGH.
• Reset all to 0x0 when rst is HIGH

Progress

• [ ] Functional simulation passed.
• [ ] Timing simulation passed.