Instruction memory design and test

[Kooscii]

inst : out STD_LOGIC_VECTOR (31 downto 0);
addr : in STD_LOGIC_VECTOR (31 downto 0));
wd : in STD_LOGIC_VECTOR (31 downto 0));
w_clk: in STD_LOGIC;

• Byte-addressing memory block
• inst = INST_MEM[addr:addr+4]
• INST_MEM[addr:addr+4] = wd when rising_edge(w_clk)

Progress

• [x] Functional simulation passed.
• [x] Timing simulation passed.

[Kooscii]

Modified the entity ports definition. Added synchronous-write function. @SandyHuang119

[Kooscii]

According to the project requirement, write function is still needed. Please add it to the design. @SandyHuang119

5. Support changing the program while your processor is running on the FPGA.